• The Transactions of the Korean Institute of Electrical Engineers B
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• v.55 no.10
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• pp.534-539
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• 2006

An integrated inductor using the low-temperature co-fired ceramics(LTCC) technology for low-power electronics was fabricated. In the inductor NiZn ferrite sheet$({\mu}_r=230)$, was embedded to increase inductance. The inductor has Ag spiral coil with 14 turns$(7turns{\times}2layers)$, a dimension of 0.6mm in width, 10um in thickness, and 0.15mm pitch. To evaluate the inductance, including the parasitic resistance, the fabricated inductor was calculated and measured. It was confirmed that calculated values were very close to the measured values. Finally as an application of the LTCC integrated inductor to low power electronic circuits, a LTCC boost DC/DC converter with 1W output power and up to 0.5MHz switching frequency using the inductor fabricated was developed.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.131-131
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• 2009

Silicon Carbide (SiC) is a material with a wide bandgap (3.26eV), a high critical electric field (~2.3MV/cm), a and a high bulk electron mobility ($\sim900cm^2/Vs$). These electronic properties allow high breakdown voltage, high-speed switching capability, and high temperature operation compared to Si devices. Although various SiC DMOSFET structures have been reported so far for optimizing performances, the effect of channel dimension on the switching performance of SiC DMOSFETs has not been extensively examined. This paper studies different channel dimensons ($L_{CH}$ : $0.5{\mu}m$, $1\;{\mu}m$, $1.5\;{\mu}m$) and their effect on the the device transient characteristics. The key design parameters for SiC DMOSFETs have been optimized and a physics-based two-dimensional (2-D) mixed device and circuit simulator by Silvaco Inc. has been used to understand the relationship. with the switching characteristics. To investigate transient characteristic of the device, mixed-mode simulation has been performed, where the solution of the basic transport equations for the 2-D device structures is directly embedded into the solution procedure for the circuit equations. We observe an increase in the turn-on and turn-off time with increasing the channel length. The switching time in 4H-SiC DMOSFETs have been found to be seriously affected by the various intrinsic parasitic components, such as gate-source capacitance and channel resistance. The intrinsic parasitic components relate to the delay time required for the carrier transit from source to drain. Therefore, improvement of switching speed in 4H-SiC DMOSFETs is essential to reduce the gate-source capacitance and channel resistance.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.12 no.3
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• pp.114-123
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• 1998

The multi-resonant converter(MRC) minimizes a parasitic oscillation by using the resonant tank circuit absorbed parasitic reactances existing in a converter circuit. So it si possible that the converter operated at a high frequency has a high efficiency because the losses are reduced. Such a MHz high frequency applications provide a high power density [W/inch3] of the converter. But the resonant voltage stress across a switch of the resonant tank circuit is 4~5 times a input voltage. This h호 voltage stress increases the conduction loss because of on-resistance of a MOSFET with higher rating. Thus, in this paper we proposed the alternated multi-resonant converter (AT MRC) differ from the clamp mode multi-resonant converter and applicated it to the forward MRC. The AT forward MRC can reduce the voltage stress to 2~3 times a input voltage by using two series input capacitor. The control circuit is simple because tow resonant switches are driven directly by the output pulse of the voltage controled oscillator. This circuit type is verified through the experimental converter with 48V input voltage, 5V/50W output voltage/power and PSpice simulation. the measured maximum voltage stress is 170V of 2.9 times the input voltage and the maximum efficiency of 81.66% is measured.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.9
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• pp.55-59
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• 2013

A new method using RF Ids determined from measured S-parameters is proposed to extract the gate-voltage dependent effective carrier velocity of bulk MOSFETs in the saturation region without additional dc Ids measurement data suffering parasitic resistance effect that becomes larger with continuous down-scaling to sub-$0.1{\mu}m$. This method also allows us to extract the carrier velocity in the saturation region without the difficult extraction of bias-dependent parasitic gate-source capacitance and effective channel length. Using the RF technique, the electron velocity overshoot exceeding the bulk saturation velocity is observed in bulk N-MOSFETs with a polysilicon gate length of $0.065{\mu}m$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.824-831
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• 2014

In this study, structural variations and overlay errors caused by multiple patterning lithography techniques to print narrow parallel metal interconnects are investigated. Resistance and capacitance parasitic of the six lines of parallel interconnects printed by double patterning lithography (DPL) and triple patterning lithography (TPL) are extracted from a field solver. Wide parameter variations both in DPL and TPL processes are analyzed to determine the impact on signal propagation. Simulations of 10% parameter variations in metal lines show delay variations up to 20% and 30% in DPL and TPL, respectively. Monte Carlo statistical analysis shows that the TPL process results in 21% larger standard variation in delay than the DPL process. Crosstalk simulations are conducted to analyze the dependency on the conditions of the neighboring wires. As expected, opposite signal transitions in the neighboring wires significantly degrade the speed of signal propagation, and the impact becomes larger in the C-worst metals patterned by the TPL process compared to those patterned by the DPL process. As a result, both DPL and TPL result in large variations in parasitic and delay. Therefore, an accurate understanding of variations in the interconnect parameters by multiple patterning lithography and adding proper margins in the circuit designs is necessary.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.12
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• pp.2655-2661
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• 2009

In this paper, an accurate noise parameters for thermal noise modeling of short channel MOSFET is derived and extracted. Fukui model for calculating the noise parameters of a MOSFET is modified by considering effects of parasitic elements in short channel, and it is compared with conventional noise model equation. In addition, for obtaining the intrinsic noise sources of devices, noise parameters(minimum noise figure $F_{min}$, equivalent noise resistance $R_n$ optimized source admittance $Y_{opt}=G_{opt}+B_{opt}$) in submicron MOSFETs is extracted. With this extraction method, the intrinsic noise parameters of MOSFET without effects of probe pad and extrinsic parasitic elements from RF noise measurements can be directly obtained.

• KOREAN JOURNAL OF CROP SCIENCE
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• v.45 no.1
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• pp.59-70
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• 2000

In nature, plant diseases, insects and parasites (hereafter called as "pest") must be co-survived. The most common expression of co-survival of a host crop to the pest can be tolerance. With tolerance, chemical uses can be minimized and it protects environment and sustains host productivity and the minimum pest survival. Tolerance can be applicable in all living organisms including crop plants, lifestocks and even human beings. Tolerant system controls pest about 90 to 95% (this pest control system often be called as horizontal or partial resistance), while the use of chemicals or selection of high resistance controls pest 100% (the most expression of this control system is vertical resistance or true resistance). Controlling or eliminating the pests by either chemicals or vertical resistance create new problems in nature and destroy the co-survial balance of pest and host. Controlling pests through tolerance can only permit co-survive of pests and hosts. Tolerance is durable and environmentally-friend. Crop cultivars based on tolerance system are different from those developed by genetically modified organism (GMO) system. The former stabilizes genetic balance of a pest and a host crop in nature while the latter destabilizes the genetic balance due to 100% control. For three decades, the author has implemented the tolerance system in breeding maize cultivars against various pests in both tropical and temperate environments. Parasitic weed Striga species known as the greatest biological problem in agriculture has even been controlled through this system. The final effect of the tolerance can be an integrated genetic pest management (IGPM) without any chemical uses and it makes co-survival of pests in nature.in nature.

• Journal of the Microelectronics and Packaging Society
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• v.30 no.3
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• pp.83-87
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• 2023

In the field of electronics and semiconductor technology, innovative semiconductor material research to replace Si is actively ongoing. However, while research on alternative materials is underway, there is a significant lack of studies regarding the relationship between 2D materials used as channels in transistors, especially parasitic resistance, and RF (radio frequency) applications. This study systematically analyzes the impact on electrical performance with a focus on various transistor structures to address this gap. The research results confirm that access resistance and contact resistance act as major factors contributing to the degradation of semiconductor device performance, particularly when highly scaled down. As the demand for high-frequency RF components continues to grow, establishing guidelines for optimizing component structures and elements to achieve desired RF performance is crucial. This study aims to contribute to this goal by providing structural guidelines that can aid in the design and development of next-generation RF transistors using 2D materials as channels.

• Progress in Superconductivity
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• v.11 no.2
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• pp.106-111
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• 2010

Sapphire resonators with $YBa_2Cu_3O_{7-\delta}$ (YBCO) endplates have provided a way to realize extremely high quality factor due to the extremely low dielectric loss of sapphire and conductive loss of YBCO films, which enables to measure the low surface resistance of superconductor films at microwave frequencies. We present microwave properties of HTS sapphire resonators designed for measuring the surface resistance of HTS films at millimeter-wave frequencies by using the two-resonance mode dielectric resonator method. Despite enhanced surface resistance ($R_S$) of YBCO films due to the quadratic frequency dependence of the $R_S$, the unloaded quality factor ($Q_0$) of the $TE_{021}$ mode sapphire resonator still appears to be well above $1\;{\times}\;10^6$ at a mm-wave frequency of 38 GHz at 10 K. However, it appears that the $TE_{012}$ mode $Q_0$ is unexpectedly low despite that the corresponding resonance peak looks uncoupled with parasitic modes. We discuss possible reasons for the unexpected results using the surface resistance at the $TE_{021}$, $TE_{012}$, and $TE_{011}$ mode frequencies.

• 한국신재생에너지학회:학술대회논문집
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• 2010.11a
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• pp.73.1-73.1
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• 2010

For the successful cold starting of a fuel cell engine, either internal of external heat supply must be made to overcome the formation of ice from water below the freezing point of water. In the present study, switchable vanadium oxide compounds as variable temperature-electrical resistance materials onto the surface of flat metallic bipolar plates have been prepared by a dip-coating technique via an aqueous sol-gel method. Subsequently, the chemical composition and micro-structure of the polycrystalline solid thin films were analyzed by X-ray diffraction, X-ray fluorescence spectroscopy, and field emission scanning electron microscopy. In addition, it was carefully measured electrical resistance hysteresis loop over a temperature range from $-20^{\circ}C$ to $80^{\circ}C$ using the four-point probe method. The experimental results revealed that the thin films was mainly composed of Karelianite $V_2O_3$ which acts as negative temperature coefficient materials. Also, it was found that thermal dissipation rate of the vanadium oxide thin films partially satisfy about 50% saving of the substantial amount of energy required for ice melting at $-20^{\circ}C$. Moreover, electrical resistances of the vanadium-based materials converge on an extremely small value similar to that of pure flat metallic bipolar plates at higher temperature, i.e. $T{\geq}40^{\circ}C$. As a consequence, experimental studies proved that it is possible to apply the variable temperature-electrical resistance material based on vanadium oxides for the cold starting enhancement of a fuel cell vehicle and minimize parasitic power loss and eliminate any necessity for external equipment for heat supply in freezing conditions.