• Title/Summary/Keyword: Parasitic parameters

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Design and Implementation of Monopole Antenna with Parasitic Element of Spiral Shape and L-Resonator (스파이럴 구조 기생 소자와 L자형 공진기를 갖는 모노폴 안테나 설계 및 구현)

  • Yoon, Kwang-Yeol;Lee, Seungwoo;Kim, Jang-Yeol;Rhee, Seung-Yeop;Kim, Nam
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.24 no.1
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    • pp.11-19
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    • 2013
  • In this paper, we designed and implemented the planar monopole antenna using the coupling effect for the multi-band characteristic. A parasitic element for the multi-band characteristic based on a rectangular patch with single resonance is inserted. Spiral shaped parasitic element is used for minimizing the antenna size and obtaining the multi-resonance characteristic. The frequency characteristics are modified and optimized by varying specific parameters. By inserting an L-shaped resonator at both sides of the feed line which connected through the via hole to the ground plane, unnecessary frequency bands are eliminated. Proposed antenna dimension is $40{\times}60{\times}1mm^3$. It is fabricated on the FR-4 substrate(${\varepsilon}_r$=4.4) using a microstrip line of $50{\Omega}$ for impedance matching. By measurement results, the characteristic of the return loss under -10 dB are 1.714~2.496 GHz, 2.977~4.301 GHz, and 4.721~6.315 GHz, and the radiation patterns have omni-directional shapes.

Parametric Study of Slow Wave Structure for Gain Enhancement and Sidelobe Suppression (이득 증가와 부엽 억제를 위한 저속파 구조의 설계변수에 대한 연구)

  • Park, Se-Been;Kang, Nyoung-Hak;Eom, Soon-Young
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.27 no.12
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    • pp.1059-1068
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    • 2016
  • This paper proposes slow wave structure(SWS) utilized to increase antenna gain of printed dipole antenna(PDA) and to suppress sidelobe level simultaneously, and makes sure of electrical characteristics of the antenna according to parameter variations of components of the slow wave structure. The printed slow wave structure which is composed of a dielectric substrate and a metal rods array is located on excited direction of the PDA, affecting the radiation pattern and its intensity. Parasitic elements of the metal rods are arrayed in narrow consistent gap and have a tendency to gradually decrease in length. In this paper, array interval, element length, and taper angle are selected as the parameter of the parasitic element that effects radiation characteristics. Magnitude and phase distribution of the electrical field are observed and analyzed for each parameter variations. On the basis of these results, while the radiation pattern is analyzed, array methods of parasitic elements of the SWS for high gain characteristics are provided. The proposed antenna is designed to be operated at the Wifi band(5.15~5.85 GHz), and parameters of the parasitic element are optimized to maximize antenna gain and suppress sidelobe. Simulated and measured results of the fabricated antenna show that it has wide bandwidth, high efficiency, high gain, and low sidelobe level.

Electrical Characterization of BGA interconnection for RF packaging (Radio Frequency 회로 모듈 BGA 패키지)

  • Kim, Dong-Young;Woo, Sang-Hyun;Choi, Soon-Shin;Jee, Yong
    • Proceedings of the IEEK Conference
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    • 2000.06b
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    • pp.96-99
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    • 2000
  • We presents a BGA(Ball Grid Array) package for RF circuit modules and extracted its electrical parameters. We constructed a BGA package of ITS(Intelligent Transportation System) RF module and examined electrical parameters with a HP5475A TDR(Time Domain Reflectometry) equipment and compared its electrical parasitic parameters with PCB RF circuits. With a BGA substrate of 3 $\times$ 3 input and output terminals, we have found that self capacitance of BGA solder ball is 68.6fF, self inductance 146pH, mutual capacitance 10.9fF and mutual inductance 16.9pH. S parameter measurement with a HP4396B Network Analyzer showed the resonance frequency of 1.55㎓ and the loss of 0.26dB. Thus, we may improve electrical performance when we use BGA package structures in the design of RF circuit modules.

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Comparative analysis of evaluation parameters in E. acervulina, E. maxima and E. tenella-infected broilers

  • Rochelle Alipio, Flores;Binh Thanh, Nguyen;Paula Leona Tayamen, Cammayo;Cherry Pambid, Fernandez-Colorado;Anindita, Roy;Suk, Kim;Woohyun, Kim;Wongi, Min
    • Journal of Veterinary Science
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    • v.23 no.6
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    • pp.91.1-91.9
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    • 2022
  • Three parameters, body weight gain (BWG), intestinal lesion score (LS) and fecal oocyst shedding, were compared in broilers infected with major parasitic species; Eimeria acervulina, E. maxima, and E. tenella. First, two- and three-week-old chickens with Eimeria infection showed LS of approximately 3, but two-week-old chickens were more correlated with BWG. Second, significant differences in BWG were observed between male and female broilers challenged with Eimeria. Finally, E. maxima-infected broilers among three Eimeria species showed a higher relationship between BWG and LS, suggesting three considerations such as genders, age and Eimeria species for Eimeria experiments.

Enhancement in the Performance of Capacitive Sensor for Oily Water Separator (유수분리기용 정전용량형 센서의 성능향상에 관한 연구)

  • Che, Woo-Seong;Kim, Kyong-Woo;Kwon, Hyu-Sang
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.10 no.10
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    • pp.1835-1841
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    • 2006
  • Demand of enhanced bilge separation sensor system has been recently increased due to the severe regulation reinforcement of MEPC(Marine Environment Production Committee). Up to date bilge separation sensor has to be extremely accurate and highly reliable. To design and build such a bilge separator. a precise oily water separation level sensor that distinguishes oil from water is critical. Three dimensional simulations have been carried out to figure out the characteristics of capacitive level sensors, which grounds the finding of the parameters required to design the sensors. The parasitic capacitance problem which is inherent to capacitive level sensors has been taken care of. This paper concludes with the future research direction that can be pursued with the newly defined parameters of the capacitive level sensors.

Direct extraction method for base-collector distributed components of HBT small-signal hybrid-p model (HBT 소신호 Hybrid-P 모델의 베이스-컬렉터 분포 성분 직접 추출방법)

  • Seo, Yeong-Seok;Seok, Eun-Yeong;Kim, Gi-Chae;Park, Yong-Wan
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.37 no.11
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    • pp.17-22
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    • 2000
  • A novel and robust direct parameter extraction method for hybrid-p equivalent circuit model of HBT is proposed. A new expression that can accurately resolve the base internal resistance from the measured S-parameters is derived, and it is not sensitive to the values of parasitic access inductance values. Based on the expression, six analytical expressions for the other parameters is developed and these expressions for hybrid-p equivalent circuit modeling ensure robust, fast, and reliable parameter extraction.

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Attenuating Effects of N-acetylcysteine (NAC) against Fish Parasiticide-induced Toxicity in Carp Cyprinus carpio (잉어(Cyprinus carpio)에서 어류 구충제에 대한 N-acetylcysteine(NAC)의 독성 저감 효과)

  • Park, Kwan-Ha
    • Korean Journal of Fisheries and Aquatic Sciences
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    • v.44 no.5
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    • pp.484-489
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    • 2011
  • This study examined whether N-acetylcysteine (NAC), a glutathione precursor, could attenuate toxic effects of three fish anti-parasitic agents, trichlorfon, hydrogen peroxide ($H_2O_2$) and formalin, all of which are known to exert side effects through free radical production. Common carp Cyprinus carpio were fed with NAC (approx. 50 mg/kg/day) for 3 consecutive days prior to anti-parasite bathing for a 24 hr period. Mortality rates were examined during this 24 hr bathing period, and selected hematological and biochemical parameters were also assessed at the termination of anti-parasite exposure. The mortality rates and plasma glucose elevations caused by all three anti-parasitics were significantly reduced by NAC pretreatment. Trichlorfon, but not $H_2O_2$ or formalin, elevated plasma levels of aspartatetransaminase (AST) and alanine-transaminase (ALT), and these elevations were attenuated by NAC. There was no change in hematocrit values in any treatment. The results provide evidence for the attenuating effects of NAC against toxicity caused by anti-parasite agents that act through free radical-producing properties. The results found in this study also suggest that NAC may be administered to fish to minimize toxicity in fish parasiticide use.

A Novel Zero-Crossing Compensation Scheme for Fixed Off-Time Controlled High Power Factor AC-DC LED Drivers

  • Chang, Changyuan;Sun, Hailong;Zhu, Wenwen;Chen, Yao;Wang, Chenhao
    • Journal of Power Electronics
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    • v.16 no.5
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    • pp.1661-1668
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    • 2016
  • A fixed off-time controlled high power factor ac-dc LED driver is proposed in this paper, which employs a novel zero-crossing-compensation (ZCC) circuit based on a fixed off-time controlled scheme. Due to the parasitic parameters of the system, the practical waveforms have a dead region. By detecting the zero-crossing boundary, the proposed ZCC circuit compensates the control signal VCOMP within the dead region, and is invalid above this region. With further optimization of the parameters KR and Kτ of the ZCC circuit, the dead zone can be eliminated and lower THD is achieved. Finally, the chip is implemented in HHNEC 0.5μm 5V/40V HVCMOS process, and a prototype circuit, delivering 7~12W of power to several 3-W LED loads, is tested under AC input voltage ranging from 85V to 265V. The test results indicate that the average total harmonic distortion (THD) of the entire system is approximately 10%, with a minimum of 5.5%, and that the power factor is above 0.955, with a maximum of 0.999.

Extraction and Analysis of Dual Gate FET Noise Parameter for High Frequency Modeling (고주파모델링을 위한 이중게이트 FET의 열잡음 파라미터 추출과 분석)

  • Kim, Gue-Chol
    • The Journal of the Korea institute of electronic communication sciences
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    • v.8 no.11
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    • pp.1633-1640
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    • 2013
  • In this paper, noise parameters for high frequency modeling of dual-gate FET are extracted and analyzed. To extract thermal noise parameter of dual gate, noise characteristics are measured by changing input impedance of noise source using Tuner, and the influence of pad parasitic elements are subtracted using open and short dummy structure. Measured results indicated that the dual-gate FET is improved the noise figure by 0.2dB compared with conventional cascode structure FET at 5GHz, and it confirmed that the noise figure has dropped due to reduction of capacitances between the drain and source, gate and drain by simulation and analysis of small-signal parameters.

Mixed-mode simulation of transient characteristics of 4H-SiC DMOSFETs (Mixed-mode simulation을 이용한 4H-SiC DMOSFETs의 채널 길이에 따른 transient 특성 분석)

  • Kang, Min-Seok;Choi, Chang-Yong;Bang, Wook;Kim, Sang-Chul;Kim, Nam-Kyun;Koo, Sang-Mo
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2009.06a
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    • pp.131-131
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    • 2009
  • Silicon Carbide (SiC) is a material with a wide bandgap (3.26eV), a high critical electric field (~2.3MV/cm), a and a high bulk electron mobility ($\sim900cm^2/Vs$). These electronic properties allow high breakdown voltage, high-speed switching capability, and high temperature operation compared to Si devices. Although various SiC DMOSFET structures have been reported so far for optimizing performances, the effect of channel dimension on the switching performance of SiC DMOSFETs has not been extensively examined. This paper studies different channel dimensons ($L_{CH}$ : $0.5{\mu}m$, $1\;{\mu}m$, $1.5\;{\mu}m$) and their effect on the the device transient characteristics. The key design parameters for SiC DMOSFETs have been optimized and a physics-based two-dimensional (2-D) mixed device and circuit simulator by Silvaco Inc. has been used to understand the relationship. with the switching characteristics. To investigate transient characteristic of the device, mixed-mode simulation has been performed, where the solution of the basic transport equations for the 2-D device structures is directly embedded into the solution procedure for the circuit equations. We observe an increase in the turn-on and turn-off time with increasing the channel length. The switching time in 4H-SiC DMOSFETs have been found to be seriously affected by the various intrinsic parasitic components, such as gate-source capacitance and channel resistance. The intrinsic parasitic components relate to the delay time required for the carrier transit from source to drain. Therefore, improvement of switching speed in 4H-SiC DMOSFETs is essential to reduce the gate-source capacitance and channel resistance.

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