• 한국전자파학회논문지
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• 제28권12호
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• pp.964-973
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• 2017

본 연구는 공통모드 초크의 기생 성분이 공통모드와 차동모드에 미치는 영향을 광대역에서 분석하고, 간단한 고주파 모델링 방법을 제시한다. 공통모드와 차동모드의 2-port 회로망을 각각 구성하여 각 모드에서의 S-parameter를 Network Analyzer로 측정하였다. 측정 결과로부터 등가회로 소자를 추출하여 고주파 등가회로를 모델링하고, 측정치와 시뮬레이션 결과를 비교함으로써 타당성을 검증하였다. 이는 정확하고 예측 가능한 EMI 필터를 설계하는데 적용될 수 있다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2005년도 전력전자학술대회 논문집
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• pp.380-384
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• 2005

Plasma display panel (PDP) has a serious thermal problem, because the luminance efficiency of the conventional PDP is about 1.5 lm/W and it is less than $3{\sim}5$ lm/W of cathode ray tube (CRT). Thus there is a need for improving the luminance efficiency of the PDP There are several approaches to improve the luminance efficiency of the PDP and we adopt the driving PDP at high frequency range from 400 kHz up to over 700 kHz. Since a PDP is regarded as an equivalent inherent capacitance, many types of sustaining drivers have been proposed and widely used to recover the energy stored in the PDP. However, these circuits have some drawbacks for driving PDP at high frequency range. In this paper, we investigate the effect of the parasitic components of PDP itself and driver when the reactive energy of panel is recovered. Various drivers are classified and evaluated whether it is suitable for high frequency driver, and finally current-fed type with do input voltage biased is proposed. This driver overcomes the effect of parasitic component in panel and driver and fully achieves ZVS of all full-bridge switches and reduces the transition time of the panel polarity.

• ETRI Journal
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• 제39권5호
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• pp.746-755
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• 2017

In this paper, an electrostatic discharge (ESD) protection circuit is designed for use as a 12 V power clamp by using a parasitic-diode-triggered silicon controlled rectifier. The breakdown voltage and trigger voltage ($V_t$) of the proposed ESD protection circuit are improved by varying the length between the n-well and the p-well, and by adding $n^+/p^+$ floating regions. Moreover, the holding voltage ($V_h$) is improved by using segmented technology. The proposed circuit was fabricated using a $0.18-{\mu}m$ bipolar-CMOS-DMOS process with a width of $100{\mu}m$. The electrical characteristics and robustness of the proposed ESD circuit were analyzed using transmission line pulse measurements and an ESD pulse generator. The electrical characteristics of the proposed circuit were also analyzed at high temperature (300 K to 500 K) to verify thermal performance. After optimization, the $V_t$ of the proposed circuit increased from 14 V to 27.8 V, and $V_h$ increased from 5.3 V to 13.6 V. The proposed circuit exhibited good robustness characteristics, enduring human-body-model surges at 7.4 kV and machine-model surges at 450 V.

• ETRI Journal
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• 제34권6호
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• pp.950-953
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• 2012

Schottky barrier single electron transistors (SB-SETs) and Schottky barrier single hole transistors (SB-SHTs) are fabricated on a 20-nm thin silicon-on-insulator substrate incorporating e-beam lithography and a conventional CMOS process technique. Erbium- and platinum-silicide are used as the source and drain material for the SB-SET and SB-SHT, respectively. The manufactured SB-SET and SB-SHT show typical transistor behavior at room temperature with a high drive current of $550{\mu}A/{\mu}m$ and $-376{\mu}A/{\mu}m$, respectively. At 7 K, these devices show SET and SHT characteristics. For the SB-SHT case, the oscillation period is 0.22 V, and the estimated quantum dot size is 16.8 nm. The transconductance is $0.05{\mu}S$ and $1.2{\mu}S$ for the SB-SET and SB-SHT, respectively. In the SB-SET and SB-SHT, a high transconductance can be easily achieved as the silicided electrode eliminates a parasitic resistance. Moreover, the SB-SET and SB-SHT can be operated as a conventional field-effect transistor (FET) and SET/SHT depending on the bias conditions, which is very promising for SET/FET hybrid applications. This work is the first report on the successful operations of SET/SHT in Schottky barrier devices.

• 한국전자파학회논문지
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• 제27권12호
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• pp.1059-1068
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• 2016

본 논문에서는 프린트 다이폴의 지향성 증가와 동시에 부엽 레벨을 억제하는 기능을 가진 저속파 구조를 제안하고 구성 설계변수의 변화에 따른 전기적 특성의 변화를 알아보고자 한다. 유전체 기판과 도체 막대의 배열로 구성된 프린트 형태의 저속파 구조는 프린트 다이폴 안테나의 여기 방향에 위치하며 안테나의 방사 패턴 및 세기에 영향을 미친다. 이 도체 막대로 된 기생소자는 좁은 간격을 가지고 일정하게 배열되며 소자의 길이는 점차 줄어드는 형상을 가진다. 따라서 본 연구에서는 저속파 구조에서 방사 성능에 영향을 줄 수 있는 변수로 기생소자 배열 간격, 소자 길이, 소자 길이의 테이퍼 각도가 고려되며, 변수들의 변화에 따른 전기장 세기 및 위상 분포가 관찰 및 분석된다. 이를 기반으로 방사패턴이 분석이 되며, 고지향성 특성을 위한 저속파 구조의 기생소자 배열 방안이 제공된다. 제안된 안테나는 Wifi 대역(5.15~5.85 GHz)에서 동작하도록 설계되며, 안테나의 이득을 극대화하고 부엽을 억제하도록 저속파 기생소자의 설계변수가 최적화된다. 제작된 안테나의 시뮬레이션 및 측정 결과 넓은 대역폭 특성을 나타내며, 높은 효율과 이득, 낮은 부엽 레벨을 갖는 것을 확인할 수 있다.

• Biomolecules & Therapeutics
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• 제24권6호
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• pp.630-637
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• 2016

The chemical components and biological activity of Camellia mistletoe, Korthalsella japonica (Loranthaceae) are relatively unknown compared to other mistletoe species. Therefore, we investigated the phytochemical properties and biological activity of this parasitic plant to provide essential preliminary scientific evidence to support and encourage its further pharmaceutical research and development. The major plant components were chromatographically isolated using high-performance liquid chromatography and their structures were elucidated using tandem mass spectrometry and nuclear magnetic resonance anlysis. Furthermore, the anti-inflammatory activity of the 70% ethanol extract of K. japonica (KJ) and its isolated components was evaluated using a nitric oxide (NO) assay and western blot analysis for inducible NO synthase (iNOS) and cyclooxygenase (COX)-2. Three flavone di-C-glycosides, lucenin-2, vicenin-2, and stellarin-2 were identified as major components of KJ, for the first time. KJ significantly inhibited NO production and reduced iNOS and COX-2 expression in lipopolysaccharide-stimulated RAW 264.7 cells at $100{\mu}g/mL$ while similar activity were observed with isolated flavone C-glycosides. In conclusion, KJ has a simple secondary metabolite profiles including flavone di-C-glycosides as major components and has a strong potential for further research and development as a source of therapeutic anti-inflammatory agents.

• 한국조명전기설비학회:학술대회논문집
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• 한국조명전기설비학회 2009년도 춘계학술대회 논문집
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• pp.384-387
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• 2009

There is an increasing demand for efficient high power/weight auxiliary power supplies for use on high speed traction application. Many new conversion techniques have been proposed to reduce the voltage and current stress of switching components, and the switching losses in the traditional pulse width modulation (PWM) converter. Especially, the phase shift full bridge zero voltage switching PWM techniques are thought must desirable for many applications because this topology permits all switching devices to operate under zero voltage switching(ZVS) by using circuit parasitic components such as leakage inductance of high frequency transformer and power device junction capacitance. The proposed topology is found to have higher efficiency than conventional soft-switching converter. Also it is easily applicable to phase shift full bridge converter by applying an energy recovery snubber consisted of fast recovery diodes and capacitors.

• 전자공학회논문지A
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• 제29A권11호
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• pp.97-106
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• 1992

In integrated circuits, protection circuits are required to protect the internal nodes from the harmful ESD(Electrostatic discharge). This paper discusses the characteristics of the circuit components in ESD protection circuitry in order to analyze the ESD phenomina, and the design methodalogy of ESD protection circuits, using test pattern with a variation of the number of diode and transistor. The test devices are fabricated using a 0.8$\mu$m CMOS process. SPICE simulation was also carried out to relate output node voltage and measured ESD voltage. With increasing number of diodes and transistors in protection circuit, the ESD voltage also increases. The ESD voltage of the bi-directional circuit for both input and output was 100-300[V], which in higher than that of only output(uni-directional) circuit. In addition, the ESD protection circuit with the diode under the pad region was useful for the reduction of chip size and parasitic resistance. In this case, ESD voltage was improved to a value about 400[V].

• 전기학회논문지
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• 제67권3호
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• pp.398-405
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• 2018

LLC resonant converter is popular with industrial fields because it can be achieved high efficiency by zero voltage switching (ZVS). As interest grew, analysis of characteristics in LLC resonant converter have been actively studied. Generally, characteristic of LLC resonant converter is analyzed based on first harmonic approximation(FHA). The FHA analysis represents the characteristics of LLC resonant converter by obtaining the series resonant operation. FHA analysis of LLC resonant converter in load condition is correct. but it is not correct in no load condition. This paper proposed analysis of characteristics considering the parasitic components to overcome the limitation of FHA and analyze no-load characteristics. The validity of the proposed method has been investigated by simulation and experimental results.

• Journal of electromagnetic engineering and science
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• 제8권2호
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• pp.47-51
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• 2008

In this paper, we present a cost effective parallel-branch spiral inductor with the enhanced quality factor and the resonance frequency. This structure is designed to improve the quality factor, but different from other fully stacked spiral inductors. The parallel-branch effect is increased by overlapping the first metal below the second metal with same direction. Measurement result shows an increased quality factor of 12 % improvement. Also, we show an octagonal parallel-branch inductor which reduces the parasitic capacitances for higher frequency applications.