• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.10
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• pp.33-46
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• 2015

In this paper, we predicts the analog and digital circuit performance of FinFETs that are scaled down following the ITRS(International technology roadmap for semiconductors). For accurate prediction of the circuit performance of scaled down devices, accurate parasitic resistance and capacitance analytical models are developed and their accuracies are within 2 % compared to 3D TCAD simulation results. The parasitic capacitance models are developed using conformal mapping, and the parasitic resistance models are enhanced to include the fin extension length($L_{ext}$) with respect to the default parasitic resistance model of BSIM-CMG. A new algorithm is developed to fit the DC characteristics of BSIM-CMG to the reference DC data. The proposed capacitance and resistance models are implemented inside BSIM-CMG to replace the default parasitic model, and SPICE simulations are performed to predict circuit performances such as $f_T$, $f_{MAX}$, ring oscillators and common source amplifier. Using the proposed parasitic capacitance and resistance model, the device and circuit performances are quantitatively predicted down to 5 nm FinFET transistors. As the FinFET technology scales, due to the improvement in both DC characteristics and the parasitic elements, the circuit performance will improve.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1607-1610
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• 2007

The measurement technology of the electrical and optical properties of CCFL and EEFL for LCD-BLU is investigated. The lamp current and voltage are affected by the leakage of parasitic capacitance. The methods using the photometer and the integrating sphere are compared to determine the lamp efficiency.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.28 no.3
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• pp.32-43
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• 2014

This paper presents the intra capacitance modeling according to the winding method, section bobbin and coil structure for hybrid choke coil capable of the EMI attenuation of broad bands from lower frequency bands to higher frequency bands and high frequency type common-mode choke coil capable of the EMI attenuation of high frequency band used in the EMI Block of LED-TV SMPS. In case of high frequency type CM choke coil, it can be explained the parasitic capacitance of A type and section bobbin type winding methods among them is much smaller than the other. The first resonant frequency of the proposed CM choke coil tends to increase as the parasitic capacitance becomes small and its impedance characteristics also show improved performance as the first resonant frequency increases. In case of hybrid choke coil using rectangular copper wire, it has investigated its parasitic capacitance compared to CM choke coil of conventional toroidal type becomes small. Also it has confirmed through the experiment results that CE margin and RE margin in frequency bands 0.5MHz to 5MHz and 30MHz to 200MHz are respectively 10dB and 15dB greater than that of conventional type in case of one stage EMI filter structure adopting hybrid choke coil compared to two stage EMI Filter structure using two of each CM choke coil used in the lower and higher frequency bands or two of CM choke coil used in only the lower frequency bands. In the future, the hybrid choke coil and CM choke coil of high frequency type show it can be practically used in not only LED/LCD-TV SMPS but also several applications such as LED Lighting, Laptop Adapter, Server Power Supply and so on.

• Journal of international Conference on Electrical Machines and Systems
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• v.2 no.1
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• pp.57-64
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• 2013

The functional characteristic of LISN circuit, which is used for measurements of conductive noise in mains power line, is basically related to frequency characteristics of passive elements like inductors used in the circuit as well as the frequency response of inductors is highly related to the resins used in the varnishing process. The significant problem in determination of an inductor's frequency characteristic is the intrinsic resistance, inductance and parasitic capacitance. In this triplet, the parasitic capacitance is the major limiting factor of inductor's frequency range. This capacitance depends on inductor design parameters and materials filling the spaces of coil like resin and its coherency after curing process. In this paper, two similar inductors were designed and built. The first inductor was not varnished while the second one was varnished with VPI technology. VPI, or Vacuum, Pressure, Impregnation technology is one of the most reliable methods performing good insulating conditions for electrical circuits and windings based on resins. The measured results show that implying varnishing technology does not significantly affect the frequency response. However, due to mechanical solidity aspects and improved environmental protection, it is better to varnish the inductors.

• The Transactions of the Korean Institute of Power Electronics
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• v.19 no.1
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• pp.8-14
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• 2014

This paper presents the intra capacitance modeling according to the winding method and section bobbin for CM choke capable of the EMI attenuation of broad bands from lower frequency bands to higher frequency bands and high frequency type common-mode choke capable of the EMI attenuation of high frequency band used in the EMI Block of LED-TV SMPS. In case of high frequency type CM choke, it can be explained the parasitic capacitance of A type and section bobbin type winding methods among them is much smaller than the other. The first resonant frequency of the proposed CM choke tends to increase as the parasitic capacitance becomes small and its impedance characteristics also show improved performance as the first resonant frequency increases. In the future, the CM chokes of high frequency type show it can be practically used in not only LED/LCD-TV SMPS but also several applications such as LED Lighting, Adapter and so on.

• Proceedings of the KIPE Conference
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• 2000.07a
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• pp.1-5
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• 2000

This paper deals with the modeling and analysis of the high voltage flyback transformer (HVFBT) often utilized in small-sized high voltage DC power supplies. The parasitic capacitance of th HVFBT with the large turns of the secondary winding causes the undesirable parasitic resonance in the transient state which produces the high current stress and limits the switching frequency of the converter. In order to analyze this phenomenon the equivalent circuit model including the parasitic capacitance is derived and the frequency characteristics are provided. The parasitic resonance in the switching states is also investigated based on this equivalent circuit model. The derived model and analysis is finally validated through the SPICE simulation and experiments.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.1
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• pp.101-107
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• 1988

This paper proposes a circuit extractor which extracts a netlist from the CIF input file cntaining the layout mask artwork informations. The circuit extractor extracts transistors and their interconnections, and calculates circuit parameter such as parasitic resistance and parasitic capacitance from the mask informations. When calculating the parasitic resistance, we consider the current flow path to reduce the errors caused by the resistance approximation. Similarly, we consider the coupling capacitance which has an effect on the circuit characteristics, when the parasitic capacitances are calculated. Therefore, using these parameter values as an input to circuit simulation, the circuit characteristics such as delay time can be estimated accurately. The presented circuit extraction algorithm uses a multiple storage quad tree as a data sturucture for storing and searching the 2-dimensional geometric data of mask artwork. Also, the proposed algorithm is technologically independent to work across a wide range of MOS technologies without any change in the algorihm.

• Proceedings of the KIEE Conference
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• 2005.04a
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• pp.55-57
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• 2005

This paper deals with the analysis of bearing current in H-bridge seven level multilevel inverter fed induction motor. In the previous researches utilized electromagnetic equations to derive the parasitic capacitance or measured capacitance parameters, but we used FEM to derive parasitic capacitances and defined the equivalent circuit parameters in our strategy. Then we compared suggested method with conventional method in 60 [Hz] no load condition.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.7
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• pp.7-16
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• 2000

This paper reports a methodology and its application for extracting cell capacitances and parasitic capacitances in a stacked DRAM cell structure by a numerical technique. To calculate the cell and parasitic capacitances, we employed finite element method (FEM), The three-dimensional DRAM cell structure is generated by solid modeling based on two-dimensional mask layout and transfer data. To obtain transfer data for generating three-dimensional simulation structure, topography simulation is performed. In this calculation, an exemplary structure comprising 4 cell capacitors with a dimension of $2.25{\times}1.75{\times}3.45{\mu}m^3$, 70,078 nodes with 395,064 tetrahedra were used in ULTRA SPARC 10 workstation. The total CPU time for the simulation was about 25 minutes, while the memory size of 201MB was required. The calculated cell capacitance is 24.34fF per cell, and the influential parasitic capacitances in a stacked DRAM cell are investigated.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.4
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• pp.821-825
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• 2004

The a-Si：H TFTs decreasing parasitic capacitance of source-drain is fabricated on glass. The structure of a-Si：H TFTs is inverted staggered. The gate electrode is formed by patterning with length of 8 ${\mu}m∼16 ${\mu}m. and width of 80∼200 ${\mu}m after depositing with gate electrode (Cr) 1500 under coming 7059 glass substrate. We have fabricated a-SiN：H, conductor, etch-stopper and photoresistor on gate electrode in sequence, respectively. The thickness of these thin films is formed with a-SiN：H (2000 ), a-Si：H(2000 ) and n+a-Si：H (500). We have deposited n+a-Si：H ,NPR(Negative Photo Resister) layer after forming pattern of Cr gate electrode by etch-stopper pattern. The NPR layer by inverting pattern of upper gate electrode is patterned and the n+a-Si：H layer is etched by the NPR pattern. The NPR layer is removed. After Cr layer is deposited and patterned, the source-drain electrode is formed. The a-Si：H TFTs decreasing parasitic capacitance of source-drain has channel length of 8 ~20 ${\mu}m and channel width of 80∼200 ${\mu}m. And it shows drain current of 8 ${\mu}A at 20 gate voltages, Ion/Ioff ratio of 108 and Vth of 4 volts.