• Title/Summary/Keyword: Parasitic BJT

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A Bandgap Reference Voltage Generator Design for Low Voltage SoC (저전압 SoC용 밴드갭 기준 전압 발생기 회로 설계)

  • Lee, Tae-Young;Lee, Jae-Hyung;Kim, Jong-Hee;Shim, Oe-Yong;Kim, Tae-Hoon;Park, Mu-Hun;Ha, Pan-Bong;Kim, Young-Hee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.12 no.1
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    • pp.137-142
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    • 2008
  • The band-gap reference voltage generator which can be operated by low voltage is proposed in this paper. The proposed BGR circuit can be realized in logic process by using parasitic NPN BJTs because a $Low-V_T$ transistors are not necessary. The proposed BGR circuit is designed and fabricated using $0.18{\mu}m$ triple-well process. The mean voltage of measured VREF is 0.72V and the three sigma$(3{\sigma})$ is 45.69mv.

Cathode Side Engineering to Raise Holding Voltage of SCR in a 0.5-㎛ 24 V CDMOS Process

  • Wang, Yang;Jin, Xiangliang;Zhou, Acheng;Yang, Liu
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.15 no.6
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    • pp.601-607
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    • 2015
  • A set of novel silicon controlled rectifier (SCR) devices' characteristics have been analyzed and verified under the electrostatic discharge (ESD) stress. A ring-shaped diffusion was added to their anode or cathode in order to improve the holding voltage (Vh) of SCR structure by creating new current discharging path and decreasing the emitter injection efficiency (${\gamma}$) of parasitic Bipolar Junction Transistor (BJT). ESD current density distribution imitated by 2-dimensional (2D) TCAD simulation demonstrated that an additional current path exists in the proposed SCR. All the related devices were investigated and characterized based on transmission line pulse (TLP) test system in a standard $0.5-{\mu}m$ 24 V CDMOS process. The proposed SCR devices with ring-shaped anode (RASCR) and ring-shaped cathode (RCSCR) own higher Vh than that of Simple SCR (S_SCR). Especially, the Vh of RCSCR has been raised above 33 V. What's more, their holding current is kept over 800 mA, which makes it possible to design power clamp with SCR structure for on chip ESD protection and keep the protected chip away from latch-up risk.

A Study on ESD Protection Circuit with High Holding Voltage with Parallel PNP and N+ difrt inserted (Parallel PNP 및 N+ drift가 삽입된 높은 홀딩전압특성을 갖는 ESD보호회로에 관한 연구)

  • Kwak, Jae-Chang
    • Journal of IKEEE
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    • v.24 no.3
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    • pp.890-894
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    • 2020
  • In this paper, we propose an ESD protection device with improved electrical characteristics through structural changes of LVTSCR, a typical ESD protection device. The proposed ESD protection device has a higher holding voltage than the existing LVTSCR by inserting a long N+ drift region and additional P-Well and N-Well, and improves the latch-up immunity, a chronic disadvantage of a general SCR-based ESD protection device. In addition, the effective base width of parasitic BJTs was set as a design variable, and the electrical characteristics of the proposed ESD protection device were verified through Synopsys' TCAD simulation so that it can be applied to the required application by applying the N-Stack technology.

A DC-DC Converter Design for OLED Display Module (OLED Display Module용 DC-DC 변환기 설계)

  • Lee, Tae-Yeong;Park, Jeong-Hun;Kim, Jeong-Hoon;Kim, Tae-Hoon;Vu, Cao Tuan;Kim, Jeong-Ho;Ban, Hyeong-Jin;Yang, Gweon;Kim, Hyoung-Gon;Ha, Pan-Bong;Kim, Young-Hee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.12 no.3
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    • pp.517-526
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    • 2008
  • A one-chip DC-DC converter circuit for OLED(Organic Light-Emitting Diode) display module of automotive clusters is newly proposed. OLED panel driving voltage circuit, which is a charge-pump type, has improved characteristics in miniaturization, low cost and EMI(Electro-Magnetic Interference) compared with DC-DC converter of PWM(Pulse Width Modulator) type. By using bulk-potential biasing circuit, charge loss due to parasitic PNP BJT formed in charge pumping, is prevented. In addition, the current dissipation in start-up circuit of band-gap reference voltage generator is reduced by 42% and the layout area of ring oscillator is reduced by using a logic voltage VLP in ring oscillator circuit using VDD supply voltage. The driving current of VDD, OLED driving voltage, is over 40mA, which is required in OLED panels. The test chip is being manufactured using $0.25{\mu}m$ high-voltage process and the layout area is $477{\mu}m{\times}653{\mu}m$.