• ETRI Journal
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• 제32권4호
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• pp.493-502
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• 2010

The operation time of an encoder is one of the critical implementation issues for satisfying the timing requirements of Long Term Evolution (LTE) systems because the encoder is based on binary operations. In this paper, we propose a design and implementation of a latency efficient encoder for LTE systems. By virtue of 8-bit parallel processing of the cyclic redundancy checking attachment, code block (CB) segmentation, and a parallel processor, we are able to construct engines for turbo codings and rate matchings of each CB in a parallel fashion. Experimental results illustrate that although the total area and clock period of the proposed scheme are 19% and 6% larger than those of a conventional method based on a serial scheme, respectively, our parallel structure decreases the latency by about 32% to 65% compared with a serial structure. In particular, our approach is more latency efficient when the encoder processes a number of CBs. In addition, we apply the proposed scheme to a real system based on LTE, so that the timing requirement for ACK/NACK transmission is met by employing the encoder based on the parallel structure.

• 한국공작기계학회논문집
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• 제13권3호
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• pp.68-75
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• 2004

Recently, need of the parallel manipulator requiring superior precision is increasing for medical application and precision manufacturing. In this study, we convert a given complex translation trajectory of the moving platform into a set of segments and hence a complex motion of the moving platform can be tractable and easily controled in a very limited workspace. In addition force exerted. to each link is minimized so that the minimized force can be transmitted to the end effector of the moving platform. An user friendly program is developed to design Gough-type 6DOF parallel manupulator based on the proposed method.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 1995년도 추계학술대회 논문집
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• pp.876-879
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• 1995

Parallel NC machines are a new generation of machine tools aimed at increasing maching accuracy and reducing part cycle time. In addition to their capacity to perform both milling and turning operations, these machine tools can perform multiple machining operations simultaneously,involving one or more parts at a time, and can completely finish a part in a single setup. Due to the lack of a computer-aided process planning system, these machines are used in industry today as dedicated, mass-production machines. This pape presents methodology for generating optimal process plan for each parallel machine tool using a genetic algorithm.

• Structural Engineering and Mechanics
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• 제23권4호
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• pp.325-337
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• 2006

A hybrid structural design and optimization methodology that combines the strengths of genetic algorithms, local search techniques, and parallel computing is developed to evolve optimal truss systems in this research effort. The primary objective that is met in evolving near-optimal or optimal structural systems using this approach is the capability of satisfying user-defined design criteria while minimizing the computational time required. The application of genetic algorithms to the design and optimization of truss systems supports conceptual design by facilitating the exploration of new design alternatives. In addition, final shape optimization of the evolved designs is supported through the refinement of member sizes using local search techniques for further improvement. The use of the hybrid approach, therefore, enhances the overall process of structural design. Parallel computing is implemented to reduce the total computation time required to obtain near-optimal designs. The support of human-computer interaction during layout optimization and local optimization is also discussed since it assists in evolving optimal truss systems that better satisfy a user's design requirements and design preferences.

• 대한전기학회논문지:전력기술부문A
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• 제48권7호
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• pp.909-915
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• 1999

In this paper, we propose an efficient VLSI architecture of Reed-Solomon(RS) decoder. To improve the speed. we develope an architecture featuring parallel and pipelined processing. To implement the parallel and pipelined processing architecture, we analyze the RS decoding algorithm and the honor's algorithm for parallel processing and we also modified the Euclid's algorithm to apply the efficient parallel structure in RS decoder. To show the proposed architecture, the performance of the proposed RS decoder is compared to Shao's and we obtain the 10 % efficiency in area and three times faster in speed when it's compared to Shao's time domain decoder. In addition, we implemented the proposed RS decoder with Altera FPGA Flex10K-50.

• 대한기계학회논문집A
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• 제28권5호
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• pp.495-502
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• 2004

In this paper, kinematic structure of parallel manipulator having 6-DOF is determined to follow the specific trajectory represented by several curves expressed by the parametric variable functions. In addition, the parallel manipulator is designed to have a high dexterity by considering a kinematic isotropy which can stabilize the motion of the moving platform in the restricted workspace.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 하계학술대회 논문집 D
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• pp.2358-2361
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• 2003

In this paper, parallel control method that enables coordinating operations of multiple mini ice storage air conditioner is proposed based on LonWorks system. The proposed parallel control method is a kind of master/slave control method based on LonTalk network communication. In the control method, master controller leading whole system operations is determined by date to avoid the disproportion of outdoor unit operations. In addition to the above, duty shift control method is proposed to avoid redundant operations of outdoor units and to equalize the operation frequencies of them. Through some simulation tests, the proposed parallel control method and the duty shift control method are evaluated and the efficiencies of them are validated by comparing with existing methods.

• 한국정보처리학회논문지
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• 제7권9호
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• pp.2827-2835
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• 2000

최근, 멀티미디어 정보처리와 같은 대규모 데이터 처리에 필수적인 입출력 시스템의 성능을 높이기 위하여 많은 관심이 집중되고 있으며, 고성능 병렬화일 시스템에 관한 연구도 이런 노력에 속한다. 본 연구에서는 고성능 병렬화일 시스템을 위한 효율적인 디스크 할당 방법을 제안한다. 즉, 병렬화일의 자료 분산(data declustering)특성을 이용하여 병렬화일에 대한 병렬도 개념을 정의하고, 이를 기반으로 여러 병렬화일들이 동시에 처리되는 경우에, 최대의 작업처리량(throughput)을 얻기 위한 각 병렬화일에 적합한 디스크상의 자료 분산 정도를 계산하는 방법을 제안한다. 또한 동시에 처리되는 병렬화일들이 많이 늘어날수록, 최대의 작업처리량을 얻기 위한 계산이 너무 복잡해지므로, 효율적인 근사 디스크 할당 알고리즘도 아울러 제안한다. 제안된 근사 알고리즘은 계산이 간단하고, 특히 입출력 작업부하(workload)가 높은 환경에서는 매우 효율적임을 보여준다. 또한 입출력 요구들의 도착 비율이 무한대일 경우, 근사 알고리즘만을 이용하여도 최대 작업처리량을 위한 최적 디스크 할당을 얻을 수 있음을 증명하였다.

• 한국컴퓨터정보학회논문지
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• 제16권5호
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• pp.1-11
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• 2011

최근 모바일 멀티미디어 기기들의 사용이 증가 하면서 고성능 멀티미디어 프로세서에 대한 필요성이 증가하고 있다. 본 논문에서는 낮은 소비전력으로 고성능 멀티미디어 애플리케이션을 구현할 수 있는 SIMD기반 병렬프로세서를 제안한다. 제안하는 병렬프로세서는 16개의 프로세싱 엘리먼트로 구성되어 있으며, 3단계 파이프라인 구조로 설계되었다. 모의실험 결과, 제안한 SIMD기반 병렬프로세서는 기존의 병렬프로세서보다 프로세싱 엘리먼트 당 상대 연산 처리량에서 높은 성능을 보였으며, 또한 동일한 130nm 테크놀리지와 720 클록주파수에서 상용 고성능 프로세서인 TI C6416보다 1.4~31.4배의 성능 향상 및 5.9~8.1배의 에너지 효율 향상을 보였다. 제안한 병렬프로세서를 하드웨어 설계언어인 verilog HDL을 이용하여 설계하였고, FPGA를 이용해 검증하였다.

• 한국정보과학회논문지:소프트웨어및응용
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• 제37권8호
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• pp.647-652
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• 2010

Esterel이라는 절차형(imperative) 동기(synchronous) 언어로부터 회로를 합성(synthesis)할 때, 하나의 동기장치(synchronizer)가 한 클럭에 중복사용되는 문제(schizophrenic parallel synchronizer)가 발생할 수 있다. 기존 컴파일러는 동기장치가 중복사용될 경우 동기장치를 복제하여 이 문제를 해결하고 있다. 본 논문은 동기장치가 중복사용되더라도 회로상/기능상 문제가 없는 조건을 제시하고, 이를 기반으로 소스코드를 분석하여 복제해야만 하는 동기장치를 찾아주는 알고리즘을 제안한다. 이 알고리즘은 컴파일러가 중복사용되는 동기장치들 중에서 꼭 복제해야만 하는 것을 알 수 있게 해 주어, Esterel 프로그램을 좀 더 작은 회로로 합성할 수 있도록 한다.