• Title/Summary/Keyword: Parallel synthesis

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A study on the Cost-effective Architecture Design of High-speed Soft-decision Viterbi Decoder for Multi-band OFDM Systems (Multi-band OFDM 시스템용 고속 연판정 비터비 디코더의 효율적인 하드웨어 구조 설계에 관한 연구)

  • Lee, Seong-Joo
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.11 s.353
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    • pp.90-97
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    • 2006
  • In this paper, we present a cost-effective architecture of high-speed soft-decision Viterbi decoder for Multi-band OFDM(MB-OFDM) systems. In the design of modem for MB-OFDM systems, a parallel processing architecture is general]y used for the reliable hardware implementation, because the systems should support a very high-speed data rate of at most 480Mbps. A Viterbi decoder also should be designed by using a parallel processing structure and support a very high-speed data rate. Therefore, we present a optimized hardware architecture for 4-way parallel processing Viterbi decoder in this paper. In order to optimize the hardware of Viterbi decoder, we compare and analyze various ACS architectures and find the optimal one among them with respect to hardware complexity and operating frequency The Viterbi decoder with a optimal hardware architecture is designed and verified by using Verilog HDL, and synthesized into gate-level circuits with TSMC 0.13um library. In the synthesis results, we find that the Viterbi decoder contains about 280K gates and works properly at the speed required in MB-OFDM systems.

Multi-scale Texture Synthesis (다중 스케일 텍스처 합성)

  • Lee, Sung-Ho;Park, Han-Wook;Lee, Jung;Kim, Chang-Hun
    • Journal of the Korea Computer Graphics Society
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    • v.14 no.2
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    • pp.19-25
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    • 2008
  • We synthesize a texture with different structures at different scales. Our technique is based on deterministic parallel synthesis allowing real-time processing on a GPU. A new coordinate transformation operator is used to construct a synthesized coordinate map based on different exemplars at different scales. The runtime overhead is minimal because this operator can be precalculated as a small lookup table. Our technique is effective for upsampling texture-rich images, because the result preserves texture detail well. In addition, a user can design a texture by coloring a low-resolution control image. This design tool can also be used for the interactive synthesis of terrain in the style of a particular exemplar, using the familiar 'raise and lower' airbrush to specify elevation.

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Physiological and Genetic Factors Controlling Streptomyces Regulatory Gene Expression Involved in Antibiotic Biosynthesis

  • Kim Eung Su
    • Proceedings of the Microbiological Society of Korea Conference
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    • 2002.10a
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    • pp.68-72
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    • 2002
  • While the biosynthetic gene cluster encoding the pigmented antibiotic actinorhodin is present in the two closely related bacterial species, Streptomyces lividans and Streptomyces coelicolor, it normally is expressed only in S. coelicolor---generating the deep blue colonies responsible for the S. coelicolor name. However, multiple copies of the afsR2 gene, which activates actinorhodin synthesis, result in the ability of S. lividansto also synthesize large amounts of actinorhodin. Here we report that the phenotypic property that historicially distinguishes these two Streptomycesspecies is determined conditionally by the carbon source used for culture. Whereas growth on glucose repressed actinorhodin production in S. lividans, culture on solid media containing glycerol as the sole carbon source dramatically increased the expression of afsR2 mRNA---leading to extensive actinorhodin synthesis by S. lividansand obliterating its phenotypic distinction from S. coelicolor. afsR2 transcription under these conditions was developmentally regulated, rising sharply at the time of aerial mycelium formation and coinciding temporally with the onset of actinorhodin production. Our results, which identify media-dependent parallel pathways that regulate actinorhodin synthesis in S. lividans, demonstrate carbon source control of actinorhodin production through the regulation of afsR2 mRNA synthesis. The nucleotide sequences of afsR2 revealed two putative important domains; the domain containing direct repeats in the middle and the domain homologous to sigma factor sequence in the C-terminal end. In this work, we constructed various sized afsR2-derivatives and compared the actinorhodin stimulating effects in S. lividans TK21. The experimental data indicate that the domain homologous to sigma factor sequence in the C-terminal end of afsR2 plays a critical role as an antibiotic stimulating function. In addition, we also observed that the single copy integration of afsR2 regulatory gene into S. lividans TK21 chromosome significantly activates antibiotic overproduction.

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Logic circuit design for high-speed computing of dynamic response in real-time hybrid simulation using FPGA-based system

  • Igarashi, Akira
    • Smart Structures and Systems
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    • v.14 no.6
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    • pp.1131-1150
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    • 2014
  • One of the issues in extending the range of applicable problems of real-time hybrid simulation is the computation speed of the simulator when large-scale computational models with a large number of DOF are used. In this study, functionality of real-time dynamic simulation of MDOF systems is achieved by creating a logic circuit that performs the step-by-step numerical time integration of the equations of motion of the system. The designed logic circuit can be implemented to an FPGA-based system; FPGA (Field Programmable Gate Array) allows large-scale parallel computing by implementing a number of arithmetic operators within the device. The operator splitting method is used as the numerical time integration scheme. The logic circuit consists of blocks of circuits that perform numerical arithmetic operations that appear in the integration scheme, including addition and multiplication of floating-point numbers, registers to store the intermediate data, and data busses connecting these elements to transmit various information including the floating-point numerical data among them. Case study on several types of linear and nonlinear MDOF system models shows that use of resource sharing in logic synthesis is crucial for effective application of FPGA to real-time dynamic simulation of structural response with time step interval of 1 ms.

Design of an HIGHT Processor Employing LFSR Architecture Allowing Parallel Outputs (병렬 출력을 갖는 LFSR 구조를 적용한 HIGHT 프로세서 설계)

  • Lee, Je-Hoon;Kim, Sang-Choon
    • Convergence Security Journal
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    • v.15 no.2
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    • pp.81-89
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    • 2015
  • HIGHT is an 64-bit block cipher, which is suitable for low power and ultra-light implementation that are used in the network that needs the consideration of security aspects. This paper presents a key scheduler that employs the presented LFSR and reverse LFSR that can generate four outputs simultaneously. In addition, we construct new key scheduler that generates 4 subkey bytes at a clock since each round block requires 4 subkey bytes at a time. Thus, the entire HIGHT processor can be controlled by single system clock with regular control mechanism. We synthesize the HIGHT processor using the VHDL. From the synthesis results, the logic size of the presented key scheduler can be reduced as 9% compared to the counterpart that is employed in the conventional HIGHT processor.

Modulation of the Somatotropic Axis in Periparturient Dairy Cows

  • Kim, Jin Wook
    • Asian-Australasian Journal of Animal Sciences
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    • v.27 no.1
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    • pp.147-154
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    • 2014
  • This review focuses on modulation of growth hormone (GH) and its downstream actions on periparturient dairy cows undergoing physiological and metabolic adaptations. During the periparturient period, cows experience a negative energy balance implicating that the feed intake does not meet the total energy demand for the onset of lactation. To regulate this metabolic condition, key hormones of somatotropic axis such as GH, IGF-I and insulin must coordinate adaptations required for the preservation of metabolic homeostasis. The hepatic GHR1A transcript and GHR protein are reduced at parturition, but recovers on postpartum. However, plasma IGF-I concentration remains low even though hepatic abundance of the GHR and IGF-I mRNA return to pre-calving value. This might be caused by alternation in IGFBPs and ALS genes, which consequently affect the plasma IGF-I stability. Plasma insulin level declines in a parallel manner with the decrease in plasma IGF-I after parturition. Increased GH stimulates the lipolytic effects and hepatic glucose synthesis to meet the energy requirement for mammary lactose synthesis, suggesting that GH antagonizes insulin-dependent glucose uptake and attenuates insulin action to decrease gluconeogenesis.

Tetrahydropteridines possess antioxidant roles to guard against glucose-induced oxidative stress in Dictyostelium discoideum

  • Park, Seon-Ok;Kim, Hye-Lim;Lee, Soo-Woong;Park, Young Shik
    • BMB Reports
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    • v.46 no.2
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    • pp.86-91
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    • 2013
  • Glucose effects on the vegetative growth of Dictyostelium discoideum Ax2 were studied by examining oxidative stress and tetrahydropteridine synthesis in cells cultured with different concentrations (0.5X, 7.7 g $L^{-1}$; 1X, 15.4 g $L^{-1}$; 2X, 30.8 g $L^{-1}$) of glucose. The growth rate was optimal in 1X cells (cells grown in 1X glucose) but was impaired drastically in 2X cells, below the level of 0.5X cells. There were glucose-dependent increases in reactive oxygen species (ROS) levels and mitochondrial dysfunction in parallel with the mRNA copy numbers of the enzymes catalyzing tetrahydropteridine synthesis and regeneration. On the other hand, both the specific activities of the enzymes and tetrahydropteridine levels in 2X cells were lower than those in 1X cells, but were higher than those in 0.5X cells. Given the antioxidant function of tetrahydropteridines and both the beneficial and harmful effects of ROS, the results suggest glucose-induced oxidative stress in Dictyostelium, a process that might originate from aerobic glycolysis, as well as a protective role of tetrahydropteridines against this stress.

A Study on Hardware Implementation of 128-bit LEA Encryption Block (128비트 LEA 암호화 블록 하드웨어 구현 연구)

  • Yoon, Gi Ha;Park, Seong Mo
    • Smart Media Journal
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    • v.4 no.4
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    • pp.39-46
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    • 2015
  • This paper describes hardware implementation of the encryption block of the '128 bit block cipher LEA' among various lightweight encryption algorithms for IoT (Internet of Things) security. Round function blocks and key-schedule blocks are designed by parallel circuits for high throughput. The encryption blocks support secret-key of 128 bits, and are designed by FSM method and 24/n stage(n=1, 2, 3, 4, 8, 12) pipeline methods. The LEA-128 encryption blocks are modeled using Verilog-HDL and implemented on FPGA, and according to the synthesis results, minimum area and maximum throughput are provided.

Minimization of Crosstalk by Optimum Synthesis of Profiles of Multiple Coupled Data Transmission Lines on Microstrip (다중결합된 마이크로스트립 데이터 전송로 자태의 최적합성을 통한 누화 최소화)

  • 박의준
    • Journal of the Korean Institute of Telematics and Electronics D
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    • v.35D no.12
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    • pp.1-11
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    • 1998
  • A line profile synthesis method is presented that minimizes the nearest-neighbor crosstalk peak level for high-speed pulse transmission in multi-coupled microstrip signal buses. We adopted the optimization technique for the reflected wave control on bus lines resulting in increasing the average spacing between strip conductors, since in a parallel-conductor bus the crosstalk energy is concentrated at the nearest neighbors of the driven line. The generalized S-matrix technique is applied for the input and output waveform prediction, and crosstalk characteristics of various nonuniform lines synthesized for increasing the average spacing are analyzed by comparing each other. Simulation results demonstrate that the Chebyshev taper with dips is adequate to significantly minimize the crosstalk peak level under the satisfactory waveform integrity since the profile is oriented to evenly reflect significant pulse spectra within the frequency range of pulse.

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A Study of Modified Parallel Feistel Structure of Data Speed-up DES (DES의 데이터 처리속도 향상을 위한 변형된 병렬 Feistel 구조에 관한 연구)

  • Lee, Seon-Keun;kIM, Hyeoung-Kyun;Kim, Hwan-Yong
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.37 no.12
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    • pp.91-97
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    • 2000
  • With the brilliant development of information communication and the rapid spread of internet, current network communication is carrying several up-to-date functions such as electronic commerce, activation of electro currency or electronic signature and will produce more advanced services in the future. Information communication network such as that electronic commerce would demand the more safe and transparent guard of network, and anticipate the more fast performance of network. In this paper, in order to meet the several demands, DES(data encryption standard) with parallel feistel structure, which feistel structure of the basic structure of DES is transformed into in parallel, is proposed. The existing feistel structure can't use pipeline method for the structural problem of DES itself-the propagation of error. therefore, this modified parallel feistel structure could improve largely the performance of DES which had to have the trade-off relation between data processing speed and data security and in addition a method proposed in SEED having adopted the modified parallel feistel structure shows more excellent secure function and/or fast processing ability. The used CAD Tool use Synopsys Ver. 1999. 10 in both of synthesis and simulation.

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