• 한국전산유체공학회지
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• 제3권1호
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• pp.22-29
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• 1998

Parallel implementation is conducted for a SIMPLER finite volume model. The present parallelism is based on domain decomposition and explicit message passing using MPI and SHMEM. Two parallel solvers to tridiagonal matrix equation are employed. The implementation is verified on the Cray T3E system for a benchmark problem of natural convection in a sidewall-heated cavity. The test results illustrate good scalability of the present parallel models. Performance issues are elaborated in view of convergence as well as conventional parallel overheads and single processor performance. The effectiveness of a localized matrix solution algorithm is demonstrated.

• International Journal of Contents
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• 제1권1호
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• pp.50-58
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• 2005

Generally, multidimensional data such as image and spatial data require large amount of storage space. There is a limit to store and manage those large amounts of data in single workstation. If we manage the data on parallel computing environment which is being actively researched these days, we can get highly improved performance. In this paper, we propose a parallel multidimensional index structure that exploits the parallelism of the parallel computing environment. The proposed index structure is nP(processor)-nxmD(disk) architecture which is the hybrid type of nP-nD and 1P-nD. Its node structure in-creases fan-out and reduces the height of an index. Also, a range search algorithm that maximizes I/O parallelism is devised, and it is applied to k-nearest neighbor queries. Through various experiments, it is shown that the proposed method outperforms other parallel index structures.

• 한국철도학회:학술대회논문집
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• 한국철도학회 2007년도 추계학술대회 논문집
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• pp.1599-1604
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• 2007

LIMs propelling the MAGLEV which has been developed in Korea have 3-series and 2-parallel connection, so that 6 LIMs per one vehicle are fed by one inverter. Thrust performance of the parallel-operated LIMs can be different from each other because of variant magnetic air gaps and electrical impedance. The thrust difference between the parallel LIMs cause a twist force on the vehicle. This paper proposes an algorithm to measure thrust of the parallel-operated LIMs. The method uses a digital signal processor(TMS320F2812), voltage and current sensors. As a result, thrust, flux and currents of the parallel-operated small LIMs which are manufactured in our laboratory are monitored by the developed measurement system.

• 한국정보처리학회논문지
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• 제4권3호
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• pp.720-730
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• 1997

본 연구에서는 격자점의 갯수나 경계 조건에 관계없이 포아송 방정식을 푸는 일반적인 프로그램을 개발하고, 수퍼 컴퓨터의 병렬 기능과 벡터 기능을 이용하여 이 프로그램 을 고속화시켰다.우리는 실제 현압에 사용되고 있는 바로토로픽 예측 모델을 이용하여 실제 태풍인 Elena의 궤도를 예측하여 보았고, 병렬화된 고속의 포아송 방정식을 사용하는 경우 상당한 시간이 절약됨을 알 수 있었다. 72시간 후의 허리케인의 궤도 예측을 시도하였다. 3000여개의 격자점 위에서 시간 간격을 16분으로 하여 실험하였는데 8개 벡터 프로세서를 갖고 있는 Aliant FX/8에서 30초만에 이루어 졌고, 3.7의 계산 효율 을 얻어냈다.

• 한국정보처리학회논문지
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• 제4권11호
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• pp.2690-2700
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• 1997

본 연구에서는 공유메모리 병렬 컴퓨터 환경에서 N개의 key를 $O(log^2N)$ 시간에 정렬 할 수 있는 병 알고리즘인 SARED-MEMORY-BS와 REDUCED-BS를 설계하였다. REDICED-BS 알고리즘은 각각 로세서에 있는 local memory를 효율적으로 사용할 수 있도록 제안한 parity전략을 사용하였다. 각각의 프로세서에 있는 local memo교를 효율적으로 사용함으로써 REDUCED-BS 알고리즘은 SHARED-MEMORY-BS 알고리즘에 비햐여 통신의 빈도수가 약 1/2정도 감소된 것으로 나타났다. 결과적으로 REDUCED-BS 알고리즘은 병렬 정렬시 통신을 감소시킴으로써 컴퓨터의 사용 효율을 향상시킬 수 있다.

• 전자공학회논문지B
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• 제32B권1호
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• pp.30-38
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• 1995

In this paper, we propose an efficient architecture for motion estimation processor which performs one of essential functions in moving picture coding algorithms. Simple control mechanism of data flow in register array which stores pixel data, parallel processing of pixel data and pipelining scheme in arithmetic umit allow this architecture to process a 352*288 pixel image at the frame rate of 30fs, which is compatable with CCITT standard H.261.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.931-934
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• 1999

For applications in multimedia to which genuine RISC microprocessors are not suitably applicable, a new generation of fast and flexible microprocessors is required. In this paper, as a technique of integrating DSP functionality in a general RISC processor, a RISC that can execute DSP extension instructions is developed to improve the performance of multimedia application execution. This processor can execute DSP instructions in parallel with the execution of ALU instructions for efficient and fast execution. In addition, the execution ability of integer instructions is improved by enhancing the RISC core itself.

• 전자공학회논문지B
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• 제32B권8호
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• pp.1085-1090
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• 1995

The Discrete Cosine Transform(DCT) is effective technique for image compression, which is widely used in the area of digital signal processing. In this paper, an efficient DCT processor is proposed and simulated by using Verilog HDL. This algorithm is improved 60% in processing speed, but it's somewhat complicate compared with Y. Arai's algorithm. This algorithm will be used efficiently for real time image processing.

• 전자공학회논문지A
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• 제32A권9호
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• pp.135-141
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• 1995

An optical digital parallel processor using Self-Pumped Phase Conjugate Mirror and liquid crystal spatial light modulator is presented and experimentally implemented. To use self-pumped PCM as memory, the mechanism for phase conjugation in two coupled interaction regions with the photorefractive crystal BaTiO$_{3}$ is investigated, especially the temporal behavior and effects of incident beam position. The optical design and implementation of matrix-vector multiplication using LCSLM and PCM memory is presented.

• 대한전기학회논문지
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• 제45권3호
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• pp.444-450
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• 1996

A digital hardware architecture for artificial neural network with learning capability is described in this paper. It is a modified hardware architecture known as HANNIBAL(Hardware Architecture for Neural Networks Implementing Back propagation Algorithm Learning). For implementing an efficient neural network hardware, we analyzed various type of multiplier which is major function block of neuro-processor cell. With this result, we design a efficient digital neural network hardware using serial/parallel multiplier, and test the operation. We also analyze the hardware efficiency with logic level simulation. (author). refs., figs., tabs.