• Journal of the Institute of Electronics Engineers of Korea SP
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• v.48 no.1
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• pp.132-140
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• 2011

Ultra-High Definition Television (U-HDTV) is a promising candidate for the next generation television. Since the U-HDTV video signal requires a huge amount of data, parallel implementation of the U-HDTV compression system is highly demanding. In the conventional parallel video codec, a video is divided into sub-sequences and the sub-sequences are independently encoded. In this paper, for efficient parallel processing, we propose a pipelined encoding structure which exploits cross-correlation among the sub-sequences. The experimental results demonstrate that the proposed technique improves the coding efficiency and provides the sub-sequences of the balanced visual quality.

• The KIPS Transactions:PartA
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• v.11A no.2
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• pp.195-202
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• 2004

This paper introduces the design or parallel Pipeline high-speed analog-to-digital converter(ADC) for the high-resolution video applications which require very precise sampling. The overall architecture of the ADC consists of 4-channel parallel time-interleaved 10-bit pipeline ADC structure a]lowing 200MSample/s sampling speed which corresponds to 4-times improvement in sampling speed per channel. Key building blocks are composed of the front-end sample-and-hold amplifier(SHA), the dynamic comparator and the 2-stage full differential operational amplifier. The 1-bit DAC, comparator and gain-2 amplifier are used internally in each stage and they were integrated into single switched capacitor architecture allowing high speed operation as well as low power consumption. In this work, the gain of operational amplifier was enhanced significantly using negative resistance element. In the ADC, a delay line Is designed for each stage using D-flip flops to align the bit signals and minimize the timing error in the conversion. The converter has the power dissipation of 280㎽ at 3.3V power supply. Measured performance includes DNL and INL of +0.7/-0.6LSB, +0.9/-0.3LSB.

• Journal of the Korea Society of Computer and Information
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• v.16 no.5
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• pp.1-11
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• 2011

As the use of mobile multimedia devices is increasing in the recent year, the needs for high-performance multimedia processors are increasing. In this regard, we propose a SIMD (Single Instruction Multiple Data) based parallel processor that supports high-performance multimedia applications with low energy consumption. The proposed parallel processor consists of 16 processing elements (PEs) and operates on a 3-stage pipelining. Experimental results indicated that the proposed parallel processor outperforms conventional parallel processors in terms of performance. In addition, our proposed parallel processor outperforms commercial high-performance TI C6416 DSP in terms of performance (1.4-31.4x better) and energy efficiency (5.9-8.1x better) with same 130nm technology and 720 clock frequency. The proposed parallel processor was developed with verilog HDL and verified with a FPGA prototype system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.12
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• pp.91-97
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• 2000

With the brilliant development of information communication and the rapid spread of internet, current network communication is carrying several up-to-date functions such as electronic commerce, activation of electro currency or electronic signature and will produce more advanced services in the future. Information communication network such as that electronic commerce would demand the more safe and transparent guard of network, and anticipate the more fast performance of network. In this paper, in order to meet the several demands, DES(data encryption standard) with parallel feistel structure, which feistel structure of the basic structure of DES is transformed into in parallel, is proposed. The existing feistel structure can't use pipeline method for the structural problem of DES itself-the propagation of error. therefore, this modified parallel feistel structure could improve largely the performance of DES which had to have the trade-off relation between data processing speed and data security and in addition a method proposed in SEED having adopted the modified parallel feistel structure shows more excellent secure function and/or fast processing ability. The used CAD Tool use Synopsys Ver. 1999. 10 in both of synthesis and simulation.

• Annual Conference of KIPS
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• 2015.04a
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• pp.114-117
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• 2015

이 논문에서는 소수 추출 방법인 Sieve of Eratosthenes 알고리즘을 병렬화하되 실행시간과 에너지 소모 면에서 개선된 효과를 얻고자 한다. 멀티코어 프로세서의 공유 메모리를 효율적으로 활용하도록 하이브리드 병렬 프로그래밍 모델을 적용하고, 부하 균등화를 정교하게 조절하도록 파이프라인 작업 방식을 도입하였다. 실험결과 이전 방식보다 연산속도가 향상되었고, 에너지 사용량도 감소함을 확인하였다.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.1386-1389
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• 1993

We are describing the architecture of a fuzzy logic controller using pulse-width-modulation (PDM) technique and a pipeline structure. Features of this controller are: A new architecture for the inference unit, reduced chip area and less I/O-pins. Additionally we present two different rule-bases: one hardwired with reduced chip-area and the other programmable for prototyping. Also an architecture of a parallel minimum-gate is shown.

• Annual Conference of KIPS
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• 2021.11a
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• pp.453-456
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• 2021

본 논문에서는 fork-join과 work stealing을 이용하여 동적 병렬처리를 수행하는 라이브러리를 구현하였다. 이 라이브러리는 병렬처리를 직관적으로 할 수 있는 함수형 프로그래밍 스타일의 파이프라인 API를 제공한다. 이를 이용한 성능 테스트에서 멀티코어를 제대로 활용하는 결과를 얻을 수 있었다. 마지막으로 blocking 작업 실행 시 병렬성 유지를 위해 추가로 개선할 수 있는 방법을 제시한다.

• Proceedings of the KIEE Conference
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• 2000.07a
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• pp.458-460
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• 2000

In this paper, we analyze the inductive coupling between overhead power transmission lines and neighbouring gas pipelines or other conductors, when they parallel to a line section in a phase-to-earth fault is assumed on the transmission line. A numerical procedure employing the finite-element method(FEM) is used in conjunction with Faraday's law, in order to predict the current in a faulted transmission line as well as the induced voltages across points on a pipeline running parallel to the faulted line and remote earth. The results lead to conclusion that may be useful to power system engineers.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.10
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• pp.36-42
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• 1997

In the whole world, the research about the VLSI implementation of motion estimation algorithm is progressed to actively full (brute force) search algorithm research with the development of systolic array possible to parallel and pipeline processing. But, because of processing time's limit in a field to handle a huge data quantily such as a high definition television, many problems are happened to full search algorithm. In the paper, as a fast processing to using parallel scheme for the serial input image data, motion estimator of systolic array structure verifying that processing time is improved in contrast to the conventional full search algorithm.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.257-260
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• 1999

We have designed a 32-bit RISC microprocessor with 16/32-bit fixed-point DSP functionality. This processor, called YRD-5, combines both general-purpose microprocessor and digital signal processor (DSP) functionality using the reduced instruction set computer (RISC) design principles. It has functional units for arithmetic operation, digital signal processing (DSP) and memory access. They operate in parallel in order to remove stall cycles after DSP and load/store instructions with one or more issue latency cycles. High performance was achieved with these parallel functional units while adopting a sophisticated 5-stage pipeline structure and an improved DSP unit.