• 제목/요약/키워드: Parallel operation algorithm

검색결과 245건 처리시간 0.024초

Performance Study of the Index-based Parallel Join

  • Jeong, Byeong-Soo;Edward Omiecinski
    • 정보기술과데이타베이스저널
    • /
    • 제2권2호
    • /
    • pp.87-109
    • /
    • 1995
  • The index file has been used a access database records effectively. The join operation in a relational database system requires a large execution time, especially in the case of handling large size tables. If the indexes are available on the joining attributes for both relations involved in the join and the join selectivity is relatively small, we can improve the execution time of the join operation. In this paper. we investigate the performance trade-offs of parallel index-based join algorithms where different indexing schemes are used. We also present a comparison of our index-based parallel join algorithms with the hash-based parallel join algorithm.

  • PDF

가중치와 준비시간을 포함한 병렬처리의 일정계획에 관한연구 (Unrelated Parallel Processing Problems with Weighted Jobs and Setup Times in Single Stage)

  • 구제현;정종윤
    • 대한산업공학회지
    • /
    • 제19권4호
    • /
    • pp.125-135
    • /
    • 1993
  • An Unrelated Parallel Processing with Weighted jobs and Setup times scheduling prolem is studied. We consider a parallel processing in which a group of processors(machines) perform a single operation on jobs of a number of different job types. The processing time of each job depends on both the job and the machine, and each job has a weight. In addition each machine requires significant setup time between processing jobs of different job types. The performance measure is to minimize total weighted flow time in order to meet the job importance and to minimize in-process inventory. We present a 0-1 Mixed Integer Programming model as an optimizing algorithm. We also present a simple heuristic algorithm. Computational results for the optimal and the heuristic algorithm are reported and the results show that the simple heuristic is quite effective and efficient.

  • PDF

병렬 파이프라인 프로세서 아키덱처의 설계 (Design of a Parallel Pipelined Processor Architecture)

  • 이상정;김광준
    • 전자공학회논문지B
    • /
    • 제32B권3호
    • /
    • pp.11-23
    • /
    • 1995
  • In this paper, a parallel pipelined processor model which acts as a small VLIW processor architecture and a scheduling algorithm for extracting instruction-level parallelism on this architecture are proposed. The proposed model has a dual-instruction mode which has maximum 4 basic operations being executed in parallel. By combining these basic operations, variable instruction set can be designed for various applications. The scheduling algorithm schedules basic operations for parallel execution and removes pipeline hazards by examining data dependency and resource conflict relations. In order to examine operation and evaluate the performance,a C compiler and a simulator are developed. By simulating various test programs with the compiler and the simulator, the characteristics and the performance result of the proposed architecture are measured.

  • PDF

A Parallel Collaborative Sphere Decoder for a MIMO Communication System

  • Koo, Jihun;Kim, Soo-Yong;Kim, Jaeseok
    • Journal of Communications and Networks
    • /
    • 제16권6호
    • /
    • pp.620-626
    • /
    • 2014
  • In this paper, we propose a parallel collaborative sphere decoder with a scalable architecture promising quasi-maximum likelyhood performance with a relatively small amount of computational resources. This design offers a hardware-friendly algorithm using a modified node operation through fixing the variable complexity of the critical path caused by the sequential nature of the conventional sphere decoder (SD). It also reduces the computational complexity compared to the fixed-complexity sphere decoder (FSD) algorithm by tree pruning using collaboratively operated node operators. A Monte Carlo simulation shows that our proposed design can be implemented using only half the parallel operators compared to the approach using an ideal fully parallel scheme such as FSD, with only about a 7% increase of the normalized decoding time for MIMO dimensions of $16{\times}16$ with 16-QAM modulation.

유전알고리즘을 이용한 디젤엔진의 연소최적화 기법에 대한 연구 (An Optimization Technique for Diesel Engine Combustion Using a Micro Genetic Algorithm)

  • 김동광;조남효;차순창;조순호
    • 한국자동차공학회논문집
    • /
    • 제12권3호
    • /
    • pp.51-58
    • /
    • 2004
  • Optimization of engine desist and operation parameters using a genetic algorithm was demonstrated for direct injection diesel engine combustion. A micro genetic algorithm and a modified KIVA-3V code were used for the analysis and optimization of the engine combustion. At each generation of the optimization step the micro genetic algorithm generated five groups of parameter sets, and the five cases of KIVA-3V analysis were to be performed either in series or in parallel. The micro genetic algorithm code was also parallelized by using MPI programming, and a multi-CPU parallel supercomputer was used to speed up the optimization process by four times. An example case for a fixed engine speed was performed with six parameters of intake swirl ratio, compression ratio, fuel injection included angle, injector hole number, SOI, and injection duration. A simultaneous optimization technique for the whole range of engine speeds would be suggested for further studies.

GPU 기반 행렬 곱셈 병렬처리 알고리즘 (Parallel Algorithm for Matrix-Matrix Multiplication on the GPU)

  • 박상근
    • 융복합기술연구소 논문집
    • /
    • 제9권1호
    • /
    • pp.1-6
    • /
    • 2019
  • Matrix multiplication is a fundamental mathematical operation that has numerous applications across most scientific fields. In this paper, we presents a parallel GPU computation algorithm for dense matrix-matrix multiplication using OpenGL compute shader, which can play a very important role as a fundamental building block for many high-performance computing applications. Experimental results on NVIDIA Quad 4000 show that the proposed algorithm runs about 208 times faster than previous CPU algorithm and achieves performance of 75 GFLOPS in single precision for dense matrices with matrix size 4,096. Such performance proves that our algorithm is practical for real applications.

Ni-Cd전지용 충전 알고리즘을 이용한 고속전철용 ZVZCS형 충전장치개발 (The Development of ZVZCS type Battery Charger for High Speed Trail Car with Ni-Cd Battery Charging Algorithm)

  • 최욱돈;이종필;이재문;김연준
    • 전력전자학회논문지
    • /
    • 제5권5호
    • /
    • pp.493-500
    • /
    • 2000
  • 고속전철용 충전기는 VVVF, CVCF, DC/DC 컨버터에 전원을 공급하고 안정성과 시스템의 신뢰성을 목적으로 하는 중요한 에너지원이다. 본 논문에서는 밧데리 충전 알고리즘과 고속전철용 ZVZCS형 밧데리 충전기의 전력회로를 포함한다. 또한 고속전철용 50kW 충전기의 최적 병렬운전과 Ni-Cd 밧데리의 충전 방법을 설명하고 실험을 통해 타당성을 입증한다.

  • PDF

연료전지 Z-소스 능동전력필터의 병렬운전 시스템 (A Parallel Operation System of the Z-Source Active Power Filter with Fuel Cells System)

  • 엄준현;정영국;임영철
    • 대한전기학회:학술대회논문집
    • /
    • 대한전기학회 2006년도 춘계학술대회 논문집 전기기기 및 에너지변환시스템부문
    • /
    • pp.372-375
    • /
    • 2006
  • This paper proposes a parallel operation system of the Z-source active power filter using one fuel cells(FC) system. The proposed system is composed of two Z-source inverters operating in parallel only one PEM(Polymer Electrolyte Membrane)FC system. Also, as the control algorithm of the active power filter, a single phase P-Q theory and PI control are adopted. The effectiveness of the proposed the system is verified by the PSIM simulation in the steady state and the transient state.

  • PDF

새로운 가상 임피던스 선정기법 기반의 적응 드룹을 이용한 직류배전용 AC/DC 컨버터의 병렬운전 (Novel Adaptive Virtual Impedance-based Droop Control for Parallel Operation of AC/DC Converter for DC Distribution)

  • 이윤성;강경민;최봉연;김미나;이훈;원충연
    • 전력전자학회:학술대회논문집
    • /
    • 전력전자학회 2020년도 전력전자학술대회
    • /
    • pp.328-329
    • /
    • 2020
  • The AC/DC converter, which connects the AC grid to the DC grid in the microgrid, is a critical component in power sharing and stable operation. Sometimes the AC/DC converters are connected in parallel to increase the transmission and reception capacity. When connected in parallel, circulating current is generated due to line impedance difference or sensor error. As a result of circulating current, there is deterioration and loss in particular PCS(Power Conversion System). In this paper, we propose droop control with novel adaptive virtual impedance for reducing circulating current. Feasibility of proposed algorithm is verified by PowerSIM simulation.

  • PDF

가변 데이터 윈도우 기법을 이용한 병행 2회선 송전선 고장점 추정 알고리즘 (Fault Location Estimation Algorithm of the parallel transmission lines using a variable data window method)

  • 정호성;윤창대;이승연;신명철
    • 대한전기학회:학술대회논문집
    • /
    • 대한전기학회 2003년도 추계학술대회 논문집 전력기술부문
    • /
    • pp.266-268
    • /
    • 2003
  • This paper proposes the Fault Location Estimation Algorithm in the parallel transmission lines. These algorithm uses a variable data window method based on least square error method to estimate fault impedance quickly. And it selects the optimal equation according to the operation situation and usable fault data for minimizing the fault estimation error effected by the zero sequence mutual coupling. After simulation result, we can see that these algorithm estimates fault location more rapidly and exactly.

  • PDF