• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.4
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• pp.48-58
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• 2016

This paper presents the high-throughput fully-parallel architecture for GF(64) (160,80) regular (2,4) non-binary LDPC (NB-LDPC) codes decoder based on the extended min sum algorithm. We exploit the NB-LDPC code that features a very low check node and variable node degree to reduce the complexity of decoder. This paper designs the fully-parallel architecture and allows the interleaving check node and variable node to increase the throughput of the decoder. We further improve the throughput by the proposed early sorting to reduce the latency of the check node operation. The proposed decoder has the latency of 37 cycles in the one decoding iteration and achieves a high throughput of 1402Mbps at 625MHz.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.39 no.3
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• pp.66-77
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• 2002

This paper deals with an implementation of the navigation parameter extraction technique using the TMS320C80 multimedia video processor (MVP). Especially, this Paper focuses on the relative position estimation algorithm which plays an important role in real-time operation of the overall system. Based on the relative position estimation algorithm using the images obtained at two locations, we develop a fast algorithm that can reduce large amount of computation time and fit into fixed-point processors. Then, the algorithm is reconfigured for parallel processing using the 4 parallel processors in the MVP. As a result, we shall demonstrate that the navigation parameter extraction system employing the MVP can operate at full-frame rate, satisfying real-time requirement of the overall system.

• Journal of Information Technology and Architecture
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• v.9 no.4
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• pp.455-464
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• 2012

Due to the recent data explosion, methods which can meet the requirement of large data analysis has been studying. This paper proposes MRIterativeBUC algorithm which enables efficient computation of large data cube by distributed parallel processing with MapReduce framework. MRIterativeBUC algorithm is developed for efficient iterative operation of the BUC method with MapReduce, and overcomes the limitations about the storage size and processing ability caused by large data cube computation. It employs the idea from the iceberg cube which computes only the interesting aspect of analysts and the distributed parallel process of cube computation by partitioning and sorting. Thus, it reduces data emission so that it can reduce network overload, processing amount on each node, and eventually the cube computation cost. The bottom-up cube computation and iterative algorithm using MapReduce, proposed in this paper, can be expanded in various way, and will make full use of many applications.

• Journal of Computational Design and Engineering
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• v.2 no.3
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• pp.183-194
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• 2015

This paper proposes a novel method for visualizing the thickness and clearance of 3D objects in a polyhedral representation. The proposed method uses the distance field of the objects in the visualization. A parallel algorithm is developed for constructing the distance field of polyhedral objects using the GPU. The distance between a voxel and the surface polygons of the model is computed many times in the distance field construction. Similar sets of polygons are usually selected as close polygons for close voxels. By using this spatial coherence, a parallel algorithm is designed to compute the distances between a cluster of close voxels and the polygons selected by the culling operation so that the fast shared memory mechanism of the GPU can be fully utilized. The thickness/clearance of the objects is visualized by distributing points on the visible surfaces of the objects and painting them with a unique color corresponding to the thickness/clearance values at those points. A modified ray casting method is developed for computing the thickness/clearance using the distance field of the objects. A system based on these algorithms can compute the distance field of complex objects within a few minutes for most cases. After the distance field construction, thickness/clearance visualization at a near interactive rate is achieved.

• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.473-473
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• 2000

This paper presents the 2-bit parallel algorithmic ADC using current mode for parallel method algorithm. It is operated by parallel conversion, 2-bit at each moment, and increase bit numbers by serial connection. The circuit operates in current mode. The comparison ratio can be controlled while working under mode operation. The circuit design used 0.8 ${\mu}{\textrm}{m}$ CMOS technology which capable to convert 2-bit in 50 ns, power consumed 0.786 nW, with input current 0-50 mA from 3V single supply. From simulation testing, the conversion rate is much faster than other method.

• Proceedings of the KIPE Conference
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• 2001.07a
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• pp.356-359
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• 2001

In this paper, the new control algorithm is proposed that compensates instantaneously the active and reactive components of the input currents by the synchronous d,q axis conversion of a single-phase current in controlling the single-phase AC/DC parallel converters for a high speed train. The leakage inductance of a transformer was used as a boost inductance and the ripple of a transformer's primary current was reduced considerably by the parallel operation of the two converters with a proper switching phase-shift. The stable and fast control response characteristic is certificated by a simulation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.162-164
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• 2010

H.264/AVC(Advanced Video Coding) is a standard for video compression. H.264/AVC provides good video quality at substantially lower bit rates than previous standards. In this papers, we propose the efficient architecture of H.264/AVC decoder using GPGPU. GPGPU can process many of operation in parallel. IQ/IDCT is possible that parallel processing in H.264/AVC decoding algorithm.

• Journal of Power Electronics
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• v.10 no.6
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• pp.686-693
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• 2010

In this paper, a fault diagnosis method based on fuzzy logic for the three-parallel power converter in a wind turbine system is presented. The method can not only detect both open and short faults but can also identify faulty switching devices without additional voltage sensors or an analysis modeling of the system. The location of a faulty switch can be indicated by six-patterns of a stator current vector and the fault switching device detection is achieved by analyzing the current vector. A fault tolerant algorithm is also presented to maintain proper performance under faulty conditions. The reliability of the proposed fault detection technique has been proven by simulations and experiments with a 10kW simulator.

• The Journal of the Korea Contents Association
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• v.7 no.1
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• pp.147-154
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• 2007

In this paper, we propose a new parallel search algorithm to acquire synchronization for UWB(Ultra Wideband) systems that reduces computation of the correlation. The conventional synchronization acquisition algorithms check all the possible signal phases simultaneously using multiple correlators. However it reduces the acquisition time, it makes high power consumption owing to increasing of correlation. The proposed algorithm divides the preamble signal to input the correlator into an m-bit bunch. We check the result of the correlation at first stage of an m-bit bunch data and predict whether it has some synchronization acquisition information or not. Thus, it eliminates the unnecessary operation and save the number of correlation. We evaluate the proposed algorithm under the AWGN and the multi-Path channel model with MATLAB. The proposed parallel search scheme reduces number of the correlation 65% on the AWGN and 20% on the multi-path fading channel.

• Proceedings of the KIEE Conference
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• 2004.11b
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• pp.190-193
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• 2004

Optimal Power Flow (OPF) is becoming more and more important in the deregulation environment of power pool and there is an urgent need of faster solution technique for on-line application. So this paper presents parallel genetic algorithm-tap search for the solution of the OPF. The control variables modeled unit active power outputs, generator-bus voltage magnitudes and transformer-tap settings. A number of functional operating constraints, such as branch flow limits, load bus boltage magnitude limits and generator reactive capabilities are included as penalties in the fitness function. In parallel GA-TS, GA operators are executed for each process. If best fitness of the GA is not changed for several generations, TS operators are executed for the upper three populations to enhance the local searching capabilities. With migration operation, best string of each node is transferred to the neighboring node after predetermined iterations are executed. For parallel computing, we developed a PC-cluster system consisting of 8 PCs. Each PC employs the 2 GHz Pentium IV CPU and is connected with others through ethernet switch based fast ethernet. To show the usefulness of the proposed method, developed algorithm has been tested and compared on an IEEE 30-bus system in the reference paper. From the simulation results, we can find that the proposed algorithm is efficient for the OPF.