• International Journal of CAD/CAM
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• v.4 no.1
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• pp.47-53
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• 2004

The subdivision surface is the limit of recursively refined polyhedral mesh. It is quite intuitive that the multi-resolution feature can be utilized to simplify generation of NC (Numerical Control) tool paths for rough machining. In this paper, a new method of parallel NC tool path generation for subdivision surfaces is presented. The basic idea of the method includes two steps: first, extending G-Buffer to a strip buffer (called S-Buffer) by dividing the working area into strips to generate NC tool paths for objects of large size; second, generating NC tool paths by parallel implementation of S-Buffer based on MPI (Message Passing Interface). Moreover, the recursion depth of the surface can be estimated for a user-specified error tolerance, so we substitute the polyhedral mesh for the limit surface during rough machining. Furthermore, we exploit the locality of S-Buffer and develop a dynamic division and load-balanced strategy to effectively parallelize S-Buffer.

• 제어로봇시스템학회:학술대회논문집
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• 1997.10a
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• pp.480-483
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• 1997

A fossil power plant can be modeled by a lot of algebraic equations and differential equations. When we simulate a large, complicated fossil power plant by a computer such as workstation or PC, it takes much time until overall equations are completely calculated. Therefore, new processing systems which have high computing speed is ultimately needed to develope real-time simulators. Vital points of real-time simulators are accuracy, computing speed, and deadline observing. In this paper, we present a enhanced strategy in which we can provide powerful computing power by parallel processing of DSP processors with communication links. We designed general purpose DSP modules, and a VME interface module. Because the DSP module is designed for general purpose, we can easily expand the parallel system by just connecting new DSP modules to the system. Additionally we propose methods about downloading programs, initial data to each DSP module via VME bus, DPRAM and processing sequences about computing and updating values between DSP modules and CPU30 board when the simulator is working.

• Journal of computational fluids engineering
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• v.4 no.3
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• pp.52-62
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• 1999

The development of a parallelized aerodynamic simulation process involving moving bodies is presented. The implementation of this process is demonstrated using a fully systemized Chimera methodology for steady and unsteady problems. This methodology consists of a Chimera hole-cutting, a new cut-paste algorithm for optimal mesh interface generation and a two-step search method for donor cell identification. It is fully automated and requires minimal user input. All procedures of the Chimera technique are parallelized on the Cray T3E using the MPI library. Two and three-dimensional examples are chosen to demonstrate the effectiveness and parallel performance of this procedure.

• The KIPS Transactions:PartA
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• v.11A no.1
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• pp.67-74
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• 2004

Most of today's parallel numerical schemes use synchronous algorithms, where some processors that have finished their tasks earlier than others must wait at synchronization points for correct computation. Hence overall performance of the system is dependent upon the speed of the slowest processor. In this paper, we det·ise a synchronous/asynchronous hybrid algorithm to accelerate convergence of the solution for finding the dominant eigenpair of a large matrix, by reducing the idle times of faster processors using MPMD programming methodology.

• Atmosphere
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• v.22 no.1
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• pp.109-115
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• 2012

We parallelized the CFD_NIMR model, which is a numerical meteorological model, for best performance on both of distributed and shared memory parallel computers. This hybrid parallelization uses MPI (Message Passing Interface) to apply horizontal 2-dimensional sub-domain out of the 3-dimensional computing domain for distributed memory system, as well as uses OpenMP (Open Multi-Processing) to apply vertical 1-dimensional sub-domain for utilizing advantage of shared memory structure. We validated the parallel model with the original sequential model, and the parallel CFD_NIMR model shows efficient speedup on the distributed and shared memory system.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1995.10a
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• pp.625-628
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• 1995

A static/implicit finite element code for sheet forming (ITAS3D) is parallelized on IBM SP 6000 multi-processor computer. Computing-load-balanced domain decomposition method and the direct solution method at each subdomain (and interface) equation are developed. The system of equations for each subdomain are constructed by condensation and calculated on each processor. Approximated operation counts are calculated to set up the nonlinear equation system for balancing the compute load on each subdomain. Th esquare cup tests with several numbers of elements are used in demonstrating the performance of this parallel implementation. This procedure are proved to be efficient for moderate number of processors, especially for large number of elements.

• Journal of the Korean Society for Industrial and Applied Mathematics
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• v.19 no.1
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• pp.57-68
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• 2015

When a straight channel formed by two parallel porous plates, through which two immiscible liquids occupying different heights are flowing a secondary motion is set up. The motion is caused by moving the upper plate with a uniform velocity about an axis perpendicular to the plates. The solutions are exact solutions. Here we discuss the effect of suction parameter and the position of interface on the flow phenomena in case of Couette flow. The velocity distributions for the primary and secondary flows have been discussed and presented graphically. The skin-friction amplitude at the upper and lower plates has been discussed for various physical parameters.

• Proceedings of the KIEE Conference
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• 2005.05a
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• pp.148-151
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• 2005

This paper proposes a high speed interface using redundant multi-valued logic for high speed communication ICs. This circuit is composed of encoding circuit that serial binary data are received and converted into parallel redundant multi-valued data, and decoding circuit that convert redundant multi-valued data to parallel binary data. Because of the multi-valued data conversion, this circuit makes it possible to achieve higher operating speeds than that of a conventional binary logic. Using this logic, a 1:4 demultiplexer (DEMUX, serial-parallel converter) IC was designed using a 0.35${\mu}m$ standard CMOS Process. Proposed demultiplexer is achieved an operating speed of 3Gb/s with a supply voltage of 3.3V and with power consumption of 48mW. Designed circuit is limited by maximum operating frequency of process. Therefore, this circuit is to achieve CMOS communication ICs with an operating speed greater than 3Gb/s in submicron process of high of operating frequency.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2001.04a
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• pp.519-522
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• 2001

In this paper, I propose double parallel manipulator for machining work. And I derive an kinematics by combining the kinematics of the central axis and the kinematics of the link train of linear actuator. The Jacobian of the central axis and the Jacobian of the link train of the linear actuators are induced by a motor algebra and they are combined to an entire Jacobian matrix to transform the velocity of the end effector to those of linear actuators. And then this paper presents the development of control system and user interface program for machining work.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.4
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• pp.235-240
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• 2007

A current-balancing segmented group-inverting transmitter is presented for multi-Gb/s single-ended parallel links. With an additional increase of 4 pins, 16-bit data is efficiently encoded to 20 pins to achieve the current balancing and eliminate the simultaneous switching noise. Since the proposed coding is a simple inversion-or-not transformation of pre-defined groups of binary data, it can be implemented with simplified logic circuits. The transmitter is designed with a $0.18{\mu}m$ CMOS technology, and simulated eye diagrams at 5Gb/s show dramatic improvements in signal integrity.