• Journal of Power Electronics
• /
• v.7 no.3
• /
• pp.238-245
• /
• 2007

This paper considers the problem of regulating the output voltage of a current doubler rectified asymmetric half-bridge (CDRAHB) DC/DC converter via fuzzy integral control. First, we model the dynamic characteristics of the CDRAHB converter with the state-space averaging method, and after introducing an additional integral state of the output regulation error, we obtain the Takagi-Sugeno (TS) fuzzy model for the augmented system. Second, the concept of parallel distributed compensation is applied to the design of the TS fuzzy integral controller, in which the state feedback gains are obtained by solving the linear matrix inequalities (LMIs). Finally, numerical simulations of the considered design method are compared to those of the conventional method, in which a compensated error amplifier is designed for the stability of the feedback control loop.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.16 no.9
• /
• pp.6247-6253
• /
• 2015

This paper presents the transient-response improved LDO regulator based on parallel error amplifiers. The proposed LDO regulator consists of an error amplifier (E/A1) which has a high gain and narrow bandwidth and a second amplifier (E/A2) which has low gain and wide bandwidth. These amplifiers are in parallel structure. Also, to improve the transient-response properties and slew-rate, some circuit block is added. Using pole-splitting technique, an external capacitor is reduced in a small on-chip size which is suitable for mobile devices. The proposed LDO has been designed and simulated using a Megna/Hynix $0.18{\mu}m$ CMOS parameters. Chip layout size is $500{\mu}m{\times}150{\mu}m$. Simulation results show 2.5 V output voltage and 100 mA load current in an input condition of 2.7 V ~ 3.3 V. Regulation Characteristic presents voltage variation of 26.1 mV and settling time of 510 ns from 100mA to 0 mA. Also, the proposed circuit has been shown voltage variation of 42.8 mV and settling time of 408 ns from 0 mA to 100 mA.

• Transactions on Electrical and Electronic Materials
• /
• v.14 no.5
• /
• pp.235-241
• /
• 2013

A low power CMOS control circuit is applied in an integrated DC-DC buck converter. The integrated converter is composed of a feedback control circuit and power block with 0.35 ${\mu}m$ CMOS process. A current-sensing circuit is integrated with the sense-FET method in the control circuit. In the current-sensing circuit, a current-mirror is used for a voltage follower in order to reduce power consumption with a smaller chip-size. The N-channel MOS acts as a switching device in the current-sensing circuit where the sensing FET is in parallel with the power MOSFET. The amplifier and comparator are designed to obtain a high gain and a fast transient time. The converter offers well-controlled output and accurately sensed inductor current. Simulation work shows that the current-sensing circuit is operated with an accuracy of higher than 90% and the transient time of the error amplifier is controlled within $75{\mu}sec$. The sensing current is in the range of a few hundred ${\mu}A$ at a frequency of 0.6~2 MHz and an input voltage of 3~5 V. The output voltage is obtained as expected with the ripple ratio within 1%.

• Proceedings of the IEEK Conference
• /
• 2000.09a
• /
• pp.951-954
• /
• 2000

In this paper, we present a multi-code parallel combinatory CDMA system using bi-orthogonal modulation to reduce envelope variation and improve bit error. .rate (BER) performance. In general, the dynamic range of the amplitude of the transmit signal is very large in the case of conventional multi-code CDMA systems, resulting in severe nonlinear distortion due to high power amplifier and thus significant BER performance degradation. The proposed system exhibits reduction of peak-to-average power ratio (PAPR) of the transmit signal amplitudes and significant performance improvement. We verify the performance of the proposed system by computer simulations under AWGN channel and flat fading channel.

• The KIPS Transactions:PartA
• /
• v.11A no.2
• /
• pp.195-202
• /
• 2004

This paper introduces the design or parallel Pipeline high-speed analog-to-digital converter(ADC) for the high-resolution video applications which require very precise sampling. The overall architecture of the ADC consists of 4-channel parallel time-interleaved 10-bit pipeline ADC structure a]lowing 200MSample/s sampling speed which corresponds to 4-times improvement in sampling speed per channel. Key building blocks are composed of the front-end sample-and-hold amplifier(SHA), the dynamic comparator and the 2-stage full differential operational amplifier. The 1-bit DAC, comparator and gain-2 amplifier are used internally in each stage and they were integrated into single switched capacitor architecture allowing high speed operation as well as low power consumption. In this work, the gain of operational amplifier was enhanced significantly using negative resistance element. In the ADC, a delay line Is designed for each stage using D-flip flops to align the bit signals and minimize the timing error in the conversion. The converter has the power dissipation of 280㎽ at 3.3V power supply. Measured performance includes DNL and INL of +0.7/-0.6LSB, +0.9/-0.3LSB.

• ETRI Journal
• /
• v.34 no.5
• /
• pp.649-654
• /
• 2012

This paper presents a novel 16-quadrature-amplitude-modulation (QAM) E-band communication system. The system can deliver 10 Gbps through eight channels with a bandwidth of 5 GHz (71-76 GHz/81-86 GHz). Each channel occupies 390 MHz and delivers 1.25 Gbps using a 16-QAM. Thus, this system can achieve a bandwidth efficiency of 3.2 bit/s/Hz. To implement the system, a driver amplifier and an RF up-/down-conversion mixer are implemented using a $0.1{\mu}m$ gallium arsenide pseudomorphic high-electron-mobility transistor (GaAs pHEMT) process. A single-IF architecture is chosen for the RF receiver. In the digital modem, 24 square root raised cosine filters and four (255, 239) Reed-Solomon forward error correction codecs are used in parallel. The modem can compensate for a carrier-frequency offset of up to 50 ppm and a symbol rate offset of up to 1 ppm. Experiment results show that the system can achieve a bit error rate of $10^{-5}$ at a signal-to-noise ratio of about 21.5 dB.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.26 no.4B
• /
• pp.520-527
• /
• 2001

육상이동위성 채널에서 고속 광대역의 정보를 효율적으로 전송하기 위한 최적 방안으로 OFDM(Orthogonal Frequency Division Multiplexing) M-ary PSK를 들 수 있다. 그러나 가입자 단말기 또는 위성중계기의 송신단 고출력 증폭기(HPA : High Power Amplifier)를 전력효율적인 비선형 mode에서 동작할 때, OFDM M-ary PSK 시스템의 최대 전력 대 평균전력의 비(PAPR : Peak-to-Average Power Ratio)가 부바송파 개수만큼 선형적으로 커져 단일 반송파 변조방식에 비해 비선형 왜곡에 의한 성능 열화가 심각하다. 본 논문에서는 이와 같은 성능 열화를 개선하기 위하여 전송채널에서 대역효율과 BER(Bit Error Rate) 성능이 우수한 PC(Parallel Combinatory) OFDM 방식과 개선된 PAPR을 가지는 PTS(Partial Transmit Sequence) OFDM 방식을 결합한 Combined PC & PTS OFDM 방식을 제안하고 그 성능을 분석하였다.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.7 no.1
• /
• pp.36-42
• /
• 2007

A low-power compact driver for multistandard physical layer is presented. The proposed driver achieves low power and small area through the voltage-mode driver with trans-impedance configuration and the novel hybrid driver,. In the voltage-mode driver, a trans-impedance configuration alleviates the problem of limited common-mode range of error amplifiers and the area and power overhead due to pre-amplifier. For a standard with extended output swing, only current sources are added in parallel with the voltage-mode driver, which is named a 'hybrid driver'. The hybrid architecture not only increases output swing but reduces overall driver area. The overall driver occupies $0.14mm^2$. Power consumptions under 3.3-V supply are 24.5 mW for the voltage-mode driver and 44.5 mW for the hybrid driver.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.29 no.5
• /
• pp.336-343
• /
• 2018

We herein present the design and fabrication of a Rx core chip operating in the X-band (10.5~13 GHz) using Win's commercial $0.25-{\mu}m$ GaAs pHEMT process technology. The X-band core chip comprises a low-noise amplifier, a four-bit phase shifter, and a serial-to-parallel data converter. The size is $1.75mm{\times}1.75mm$, which is the state-of-the-art size. The gain and noise figure are more than 10 dB but less than 2 dB, and both the input and output return losses are less than 10 dB. The RMS phase error is less than $5^{\circ}$, and the P1dB is 2 dBm at 12.5 GHz, the performance of which is equivalent to other GaAs core chips. The fabricated core chip was packaged in a QFN package type with a size of $3mm{\times}3mm$ for the convenience of assembly. We confirmed that the performance of the packaged core chip was almost the same as that of the chip itself.

• Proceedings of the KIEE Conference
• /
• 2002.07b
• /
• pp.1094-1096
• /
• 2002

A new technique for improving the efficiency of single-phase high-frequency boost converter is proposed. This converter includes an additional low-frequency boost converter which is connected to the main high-frequency switching device in parallel. The additional converter is controlled at lower frequency. Most of the current flows in the low-frequency switch and so, high-frequency switching loss is greatly reduced accordingly. Both switching device are controlled by a simple method; each controller consists of a comparator, a frequency generator and an error amplifier. The converter works cooperatively in high efficiency and acts as if it were a conventional high-frequency boost converter with one switching device, The proposed method is verified by simulation and experiment. This paper describes the converter configuration and design, and discusses the steady-state performance concerning the switching loss reduction and efficiency improvement.