• Proceedings of the KIPE Conference
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• 1998.07a
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• pp.90-94
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• 1998

The parallel inverter is popularly used because of its fault-tolerance capability, high-current outputs at constant voltages and system modularity. The conventional parallel inverter usually employes active and reactive power control or frequency and voltage droop control. However, these approaches have the disadvantages that the response time of parallel inverter control is slow against load and system parameter variation to calculate active, reactive power, frequency and voltage. This paper describes a novel control scheme for power equalization in parallel connected inverter. The proposed scheme has a fast power balance control response, a simplicity of implementation, and inherent peak current limiting capability since it employes a instantaneous current/voltage control with output voltage and current balance and output voltage regulation. A design procedure for the proposed parallel inverter controller is presented. Futhermore, the proposed control scheme is verified through the simulation in various cases such as the system parameter variation, the control parameter variation and the nonlinear load condition.

• Proceedings of the KIPE Conference
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• 1998.10a
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• pp.176-181
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• 1998

The parallel inverter is popularly used because of its fault-tolerance capability, high-current outputs at constant voltages and system modularity. The conventional parallel inverter usually employs active and reactive power control of frequency and voltage droop control. However, these approaches have the disadvantages that the response time of parallel inverter control is slow against load and system parameter variation to calculate active, reactive power, frequency and voltage. This paper describes a novel control scheme for power equalization in parallel-connected inverter. The proposed scheme has a fast power balance control response, a simplicity of implementation, and inherent peak current limiting capability since it employees an instantaneous current/voltage control with output voltage and current balance and output voltage regulation. A design procedure for the proposed parallel inverter controller is presented. Furthermore, the proposed control scheme is verified through the experiment in various cases such as the system parameter variation, the control parameter variation and the nonlinear load condition.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.3A
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• pp.214-220
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• 2006

In this paper, we propose the transmit power controlled adaptive modulated OFDM with frequency symbol spreading and equalization(TPC-AMS/FSS-OFDM) system. In the transmitter of the TPC-AMS/FSS-OFDM, each SP transformed signal is spread by orthogonal spreading codes and combined, so the detected signals obtain the same SINR(signal interference to noise ration) for each frequency symbol spreading block. In this case, we can assign the same modulation level and transmit power for each frequency symbol spreading block. Thus, the proposed system provides the increased throughput performance with reducing the total transmit power, FBI and MLI.

• Journal of Communications and Networks
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• v.6 no.1
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• pp.19-25
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• 2004

In this paper, we present a trellis-based blind channel estimation and equalization technique coupling two kinds of adaptive Viterbi algorithms. First, the initial blind channel estimation is accomplished by incorporating the list parallel Viterbi algorithm with the least mean square (LMS) updating approach. In this operation, multiple trellis mappings are preserved simultaneously and ranked in terms of path metrics. Equivalently, multiple channel estimates are maintained and updated once a single symbol is received. Second, the best channel estimate from the above operation will be adopted to set up the whole trellis. The conventional adaptive Viterbi algorithm is then applied to detect the signal and further update the channel estimate alternately. A small delay is introduced for the symbol detection and the decision feedback to smooth the noise impact. An automatic switch between the above two operations is also proposed by exploiting the evolution of path metrics and the linear constraint inherent in the trellis mapping. Simulation has shown an overall excellent performance of the proposed scheme in terms of mean square error (MSE) for channel estimation, robustness to the initial channel guess, computational complexity, and channel equalization.

• The KIPS Transactions:PartB
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• v.13B no.3 s.106
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• pp.223-230
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• 2006

A window-based image processing is an elementary part of image processing area. Because window-based image processing is computationally intensive and data intensive, it is hard to perform ail of the operations of a window-based image processing in real-time by using a software program on general-purpose computers. This paper proposes a parallel hardware architecture that can perform a window-based image processing in real-time using FPGA(Field Programmable Gate Array). A dynamic threshold circuit and a local histogram equalization circuit of the proposed architecture are designed using VHDL(VHSIC Hardware Description Language) and implemented with an FPGA. The performances of both implementations are measured.

• ETRI Journal
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• v.37 no.5
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• pp.906-916
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• 2015

High-speed I/O channels require adaptive techniques to optimize the settings for filter tap weights at decision feedback equalization (DFE) read channels to compensate for channel inter-symbol interference (ISI) and crosstalk from multiple adjacent channels. Both ISI and crosstalk tend to vary with channel length, process, and temperature variations. Individually optimizing parameters such as those just mentioned leads to suboptimal solutions. We propose a joint optimization technique for crosstalk cancellation (XTC) at DFE to compensate for both ISI and XTC in high-speed I/O channels. The technique is used to compensate for between 15.7 dB and 19.7 dB of channel loss combined with a variety of crosstalk strengths from $60mV_{p-p}$ to $180mV_{p-p}$ adaptively, where the transmit non-return-to-zero signal amplitude is a constant $500mV_{p-p}$.

• The Transactions of the Korea Information Processing Society
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• v.4 no.2
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• pp.338-348
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• 1997

In this pater, we first propose a data distribution framework to resolve load imbalance and bucket oerflow in parallel hash join.Using the histogram equalization technique, the framework transforms a histogram of skewed data to the desired uniform distribution that corresponds to the relative computing power of node processors in the system.Next we propose an effcient parallel hash join algorithm for handing skwed data based on the proposed data distribution methodology.For performance comparison of our algorithm with other hash join algorithms.we perform similation experiments and actual exeution on COREDB database computer with 8-node hyperube architecture. In these experiments, skwed data distebution of the join atteibute is modeled using a Zipf-like distribution.The perfomance studies undicate that our algorithm outperforms other algorithms in the skewed cases.

• Journal of Industrial Technology
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• v.15
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• pp.223-233
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• 1995

본 논문에서는 데이터 분포가 편재된 상황하에서 부하의 불균형과 버켓 오벌플로우 문제를 해결하기 위해 히스토그램 변환 기법을 이용한 데이터 분산 방법과 이를 기초로 한 병렬 결합 알고리즘을 제안한다. 제안된 알고리즘의 성능은 시뮬레이션과 하이퍼큐브형 병렬 컴퓨터 상에서 실험적인 방법에 의하여 분석되었다. 그 결과 제안된 알고리즘이 기본의 해쉬 결합 방법보다 우수함을 보인다.

• Proceedings of the KIPE Conference
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• 1998.10a
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• pp.554-559
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• 1998

Equalizing the state of charge of cell that affects the charge/discharge quality and efficiency of the battery through the charge/discharge characteristic experiments of battery source, we develope the high efficiency charge/discharge system which would be used in serial HEV with the constant engine-generator output. For this, establishes the electrical model of Ni-MH battery appropriate to the high efficiency charge/discharge conditions. There is no model of Ni-MH cell, so we used Ni-Cd model and obtain the Ni-MH model through the experiment. A reason that each cell has the same charge/discharge property for applying the cell model to serial/parallel connected battery source extensively is needed. Therefore, in this paper, propose the Ni-MH charger/discharger has the equalization charging function and selectable cut-off function.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.11 no.5
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• pp.27-33
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• 2011

In digital communication system that the Modified Constant Modulus Algorithm (MCMA) reduced the use of the adaptive equalization algorithm to combat the Inter-symbol Interference (ISI). MCMA is relatively brief operation. The major point of MCMA that it only achieves moderate convergence rate and steady state mean square error (MSE). In this paper suggest, MCMA equalization improve the performance with parallel structure. It combines Modified Constant Modulus Algorithm(MCMA) and Modified Decision Directed(MDD) algorithm. By exploiting the inherent structural relationship between the 4-QAM signal's coordinates and 16-QAM signal's coordinates, another style of cost function for Modified Constant Modulus Algorithm(MCMA) is defined and If it happen to offset of received signals and MCMA is poor performance in order to overcome this because the paper combines apply for MCMA and MDD(Modified Decision Direct) algorithm. By computer simulation, we confirmed that the proposed PMCMA-MDD algorithm has the fater convergence rate and steady mean square error than the conventional MCMA.