• The Journal of the Korea institute of electronic communication sciences
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• v.17 no.1
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• pp.71-76
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• 2022

Since brightness is proportional to the operating current, a method of connecting several LEDs in series and driving with a constant current source is widely used for driving circuits of LED lights. Because several LEDs are connected in series, if some LEDs open due to a fault, the current path is broken and all other LEDs connected in series are turned off. In this paper, we designed a circuit to solve this problem by connecting a Zener diode having a breakdown voltage of about 0.4V higher than the LED operating voltage in parallel with each LED to create a current bypass in case of LED failure. Through simulations and experiments, it was confirmed that the current of the Zener diode hardly flows when the LED is operating normally, and that the Zener diode stably operates as a current bypass when the LED fails.

• Nuclear Engineering and Technology
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• v.54 no.7
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• pp.2444-2452
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• 2022

The field-programmable gate array (FPGA) is gaining popularity in industrial automation such as nuclear power plant instrumentation and control (I&C) systems due to the benefits of having non-existence of operating system, minimum software errors, and minimum common reason failures. Separate functions can be processed individually and in parallel on the same integrated circuit using FPGAs in comparison to the conventional microprocessor-based systems used in any plant operations. The use of FPGAs offers the potential to minimize complexity and the accompanying difficulty of securing regulatory approval, as well as provide superior protection against obsolescence. Wireless sensor networks (WSNs) are a new technology for acquiring and processing plant data wirelessly in which sensor nodes are configured for real-time signal processing, data acquisition, and monitoring. ZigBee (IEEE 802.15.4) is an open worldwide standard for minimum power, low-cost machine-to-machine (M2M), and internet of things (IoT) enabled wireless network communication. It is always a challenge to follow the specific topology when different Zigbee nodes are placed in a large network such as a plant. The research article focuses on the hardware chip design of different topological structures supported by ZigBee that can be used for monitoring and controlling the different operations of the plant and evaluates the performance in Vitex-5 FPGA hardware. The research work presents a strategy for configuring FPGA with ZigBee sensor nodes when communicating in a large area such as an industrial plant for real-time monitoring.

• Journal of IKEEE
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• v.25 no.4
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• pp.741-749
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• 2021

This paper presents the current-fed type LLC AC to DC high frequency resonant converter capable of ZVZCS(Zero-Voltage and Zero-Current Switching). The current-fed type LLC AC to DC high frequency resonant converter proposed in this paper could operate not only in ZVS(Zero-Voltage Switching) operation by connecting the resonant capacitors(C₁, C₂) in parallel across the switching devices but also in ZCS(Zero-Current Switching) operation of the secondary diode. The ZVS and ZCS operations can reduce the turn-on loss of the switching devices and the turn-off loss of the secondary diodes, respectively. The circuit analysis of current-fed type LLC AC to DC high frequency resonant converter proposed in this paper is addressed generally by adopting the normalized parameters. The operating characteristics of proposed LLC AC to DC high frequency resonant converter were also evaluated by using the normalized control parameters such as the normalized control frequency(μ), the normalized load resistor(λ) and so on. Based on the characteristic values through the characteristics of evaluation, an example of the design method of proposed LLC AC to DC high frequency resonant converter is suggested, and the validity of the theoretical analysis is confirmed using the experimental results and PSIM simulation.

• International Journal of Aerospace System Engineering
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• v.9 no.2
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• pp.1-9
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• 2022

The NEA release mechanism is used to provide restraint and release functions with low shock for critical deployment operations on solar arrays after launch. The GK3 solar array consists of 2 wings and 6 hold down points per panel. The NEA SSD9103S1 is a part of the GK3 solar array hold-down and release mechanism. Each NEA unit is equipped with two Z-diodes which provide power to a NEA unit connected in series after actuation of the fuse wire. This paper presents the hot firing test results of a quadrature NEA SSD9103S1 configuration. One output powers a maximum of 4 NEA SSD9103S1 units simultaneously. The necessary actuation pulse duration has been determined to meet margin requirement for thermal energy of minimum 4. Actuation thermal energy difference is about 6.6% between each half of two fired serial NEAs. Thermal energy margin at worst case is minimum 5.9 in case of an actuation pulse duration of 500 ms. Two series Zener impedance depend on current applied has been characterized by an additional actuation after all fuse wires are open circuit. Total number of actuation commands to the GK3 NEA unit reduce drastically from 24 in case of single NEA configuration down to 8 in case of parallel and quadrature NEA configurations. It can be accommodated by the existing HP2U Pyro design without any impact.

• Journal of the Korean Society of Safety
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• v.38 no.4
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• pp.8-14
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• 2023

This study presents the characteristics of short circuits (SCs) caused by excessive currents in high-voltage cables used in electric vehicles and emphasizes the need to calculate the cross-sectional areas of these cables according to the SC current. Three direct current power supplies were connected in parallel to test the SC characteristics caused by excessive currents, and a timer and a magnetic contactor were used to deliver the conduction time and SC current. A circular infrared-radiation heater was used to test the temperature-dependent SC characteristics, a thermocouple was used to measure the temperature, and a shunt resistor was used to measure the current. As the SC current increased, the fusing time of the cable decreased. Additionally, a high-voltage cable (with an area of 16 mm² ) used in electric vehicles fused when a current (approximately equal to 55 times the allowable current) flowed for 0.2 s (operating time of the protective device). When the SC current is 10 kA, the cable may fuse during the operating time of the protective device, thus creating a fire hazard. In electric vehicles, the size of the SC current increases in proportion to the capacity of the battery. Thus, the cross-sectional areas of the cables used should be calculated accordingly, and cable operations should be properly coordinated with the surrounding protective devices.

• Journal of Korean Elementary Science Education
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• v.24 no.3
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• pp.259-267
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• 2005

This study was to investigate the elementary students' preconception on the brightness of electric bulb and degree of consistency on their preconceptions. Participants were 160 students of fifth graders in Seoul area. They had already teamed about the brightness of series circuit and parallel circuit of batteries. After they solved six problems in the same context, we provided them a pair of circuit which was an anomalous situation. And then they conducted CCLT (Cognitive Conflict Level Test). Elementary school students showed various preconceptions when they explained the light of bulb of two Simple electric Circuits. Many Students Consistently Showed the Scientific misconceptions like 'the light of bulb of two simple electric circuits was that the more batteries and the fewer bulbs were brighter.' The level of consistency that students presented scientific misconceptions was grouped all of four, such as 'high, middle, low, and nothing.' Therefore the higher scientific achievement they have, the higher consistency they have. As the students had high consistency level, they revealed high cognitive conflict level significantly. This high consistency will help them to change their preconception on the brightness of electric bulb and their cognitive conflict.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.12
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• pp.1970-1982
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• 1993

This paper describes an efficient array algorithm for parallel computation of vector-radix two-dimensional (2-D) fast discrete cosine transform (VR-FCT), and its VLSI implementation. By mapping the 2-D VR-FCT onto a 2-D array of processing elements (PEs), the butterfly structure of the VR-FCT can be efficiently importanted with high concurrency and local communication geometry. The proposed array algorithm features architectural modularity, regularity and locality, so that it is very suitable for VLSI realization. Also, no transposition memory is required, which is invitable in the conventional row-column decomposition approach. It has the time complexity of O(N+Nnzp-log2N) for (N*N) 2-D DCT, where Nnzd is the number of non-zero digits in canonic-signed digit(CSD) code, By adopting the CSD arithmetic in circuit desine, the number of addition is reduced by about 30%, as compared to the 2`s complement arithmetic. The computational accuracy analysis for finite wordlength processing is presented. From simulation result, it is estimated that (8*8) 2-D DCT (with Nnzp=4) can be computed in about 0.88 sec at 50 MHz clock frequency, resulting in the throughput rate of about 72 Mega pixels per second.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.9C
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• pp.861-870
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• 2002

In this paper, with targeting on the drawback of RSA of operation speed, a new 1024-bit RSA cryptosystem has been proposed and implemented in hardware to increase the operational speed and perform the variable-length encryption. The proposed cryptosystem mainly consists of the modular exponentiation part and the modular multiplication part. For the modular exponentiation, the RL-binary method, which performs squaring and modular multiplying in parallel, was improved, and then applied. And 4-stage CSA structure and radix-4 booth algorithm were applied to enhance the variable-length operation and reduce the number of partial product in modular multiplication arithmetic. The proposed RSA cryptosystem which can calculate at most 1024 bits at a tittle was mapped into the integrated circuit using the Hynix Phantom Cell Library for Hynix 0.35㎛ 2-Poly 4-Metal CMOS process. Also, the result of software implementation, which had been programmed prior to the hardware research, has been used to verify the operation of the hardware system. The size of the result from the hardware implementation was about 190k gate count and the operational clock frequency was 150㎒. By considering a variable-length of modulus number, the baud rate of the proposed scheme is one and half times faster than the previous works. Therefore, the proposed high speed variable-length RSA cryptosystem should be able to be used in various information security system which requires high speed operation.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.11
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• pp.51-62
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• 2003

This paper presents a novel survivor memeory management and decoding techniques with sequential backward state transition control in the trace back Viterbi decoder. The Viterbi algorithm is an maximum likelihood decoding scheme to estimate the likelihood of encoder state for channel error detection and correction. This scheme is applied to a broad range of digital communication such as intersymbol interference removing and channel equalization. In order to achieve the area-efficiency VLSI chip design with high throughput in the Viterbi decoder in which recursive operation is implied, more research is required to obtain a simple systematic parallel ACS architecture and surviver memory management. As a method of solution to the problem, this paper addresses a progressive decoding algorithm with sequential backward state transition control in the trace back Viterbi decoder. Compared to the conventional trace back decoding techniques, the required total memory can be greatly reduced in the proposed method. Furthermore, the proposed method can be implemented with a simple pipelined structure with systolic array type architecture. The implementation of the peripheral logic circuit for the control of memory access is not required, and memory access bandwidth can be reduced Therefore, the proposed method has characteristics of high area-efficiency and low power consumption with high throughput. Finally, the examples of decoding results for the received data with channel noise and application result are provided to evaluate the efficiency of the proposed method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.13-20
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• 2008

This paper describes the design of low power 12bit Digital-to-Analog Converter(D/A Converter) using Pseudo-Segmentation method which shows the conversion rate of 80MHz and the power supply of 1.8V with 0.18um CMOS n-well 1-poly 6-metal process for advanced wireless communication system. Pseudo-segmentation method used in binary decoder consists of simple parallel buffer is employed for low power because of simpler configuration than that of thermometer decoder. Also, using deglitch circuit and swing reduced drivel reduces a switching noise. The measurement results of the proposed low power 12bit 80MHz CMOS D/A Converter shows SFDR is 66.01dBc at sampling frequency 80MHz, input frequency 1MHz and ENOB is 10.67bit. Integral nonlinearity(INL) / Differential nonlinearity(DNL) have been measured ${\pm}1.6LSB/{\pm}1.2LSB$. Glich energy is measured $49pV{\cdot}s$. Power dissipation is 46.8mW at 80MHz(Maximum sampling frequency) at a 1.8V power supply.