• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.9
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• pp.11-20
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• 1998

High-speed complex-number arithmetic units are essential to baseband signal processing of modern digital communication systems such as channel equalization, timing recovery, modulation and demodulation. In this paper, a new complex-number multiplication algorithm is proposed, which is based on redundant binary (RB) arithmetic combined with radix-4 Booth recoding scheme. The proposed algorithm reduces the number of partial product by one-half as compared with the conventional direct method using real-number multipliers and adders. It also leads to a highly parallel architecture and simplified circuit, resulting in high-speed operation and low power dissipation. To demonstrate the proposed algorithm, a prototype complex-number multiplier-accumulator (CMAC) core with 10-bit operands has been designed using 0.8-$\mu\textrm{m}$ N-Well CMOS technology. The designed CMAC core contains about 18,000 transistors on the area of about 1.60 ${\times}$ 1.93 $\textrm{mm}^2$. The functional and speed test results show that it can operate with 120-MHz clock at V$\sub$DD/=3.3-V, and its power consumption is given to about 63-mW.

• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.6
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• pp.1429-1435
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• 2012

DC-DC converter commonly used in photovoltaic systems, fuel cell systems and electric vehicles is a boost converter. The interleaved boost converter, connected in parallel by several boost converters and operated by the phase difference to reduce the input and output current ripple, has been widely used in recent years. Because of small input and output current ripples, the circuit can reduce the size of the input and output capacitors. Thus, instead of conventional electrolytic capacitor, the film capacitor with high reliability can be used and this is the life and reliability of the entire system can be improved. In this paper, the output current ripple formulas of the multi-stage interleaved boost converter are derived, and the characteristics in accordance with duty are found out. In order to verify the abovementioned contents, the derived results will make a comparison with the calculated values by using PSIM tool.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.63 no.4
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• pp.361-367
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• 2014

This paper is related to a new solar power conditioner for a built-in step-up chopper function. In the first step-up chopper proposed solar PV power conditioner for mutually connected in series with the input voltage of the bypass diodes are respectively connected to the positive terminal should install the mutual boosting chopper diode connected in series with the boost chopper switching element between the two power supply and at the same time the first and the second was connected to a second diode and a resonance inductor and a snubber capacitor in series with each other. And the common connection point between the bypass diode and the step-up chopper and the step-up chopper diode common connection point of the switching elements of the input voltage was set to the boost inductor for storing energy. In addition, between the step-up chopper and the step-up chopper diode and a switching element of a joint connection point of the first auxiliary diode and the second common connection point of the auxiliary diode was provided, the resonance capacitor. Between the step-up chopper and the step-up chopper diode and a switching element of a joint connection point and the common connection point of the resonance inductor snubber capacitor and connecting the third secondary diode, between two power supply lines is characterized by configuring the DC link capacitor bus lines in parallel. Therefore, it is possible to suppress the switching loss through, DC link bus lines, as well as there could seek miniaturization and weight reduction of the power conditioner itself by using a common capacitor of the non-polar non-polar electrolytic capacitor having a capacitor, the service life of the circuit can be extended and it is possible to greatly reduce the loss can be greatly improve the reliability of the product and the operation of the product itself.

• Proceedings of the KIPE Conference
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• 2005.07a
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• pp.774-777
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• 2005

In this paper, a constant frequency phase shifting PWM controlled voltage source full bridge-type series load resonant high-frequency inverter using the IGBT power modules is presented for innovative consumer electromagnetic induction heating applications such as a hot water producer, steamer and super heated steamer. The full bridge arm side link passive quasi-resonant capacitor snubbers in parallel with the each power semiconductor device and high frequency AC load side linked active edge inductive snubber-assisted series load resonant tank soft switching inverter with a constant frequency phase shifted PWM control scheme is discussed and evaluated on the basis of the simulation and experimental results. It is proved from a practical point of view that the series load resonant and edge resonant hybrid high-frequency soft switching PWM inverter topology, what is called class DE type. including the variable-power variable-frequency(VPVF) regulation function can expand zero voltage soft switching commutation range even under low output power setting ranges, which is more suitable and acceptable for induction heated dual packs fluid heater developed newly for consumer power utilizations. Furthermore, even in the lower output power regulation mode of this high-frequency load resonant tank high frequency inverter circuit it is verified that this inverter can achieve ZVS with the aid of the single auxiliary inductor snubber.

• The Transactions of the Korean Institute of Power Electronics
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• v.15 no.3
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• pp.218-225
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• 2010

This paper deals with a method to minimize the welding time for an AC spot welding system. The spot welding system using a conventional SCR type circuit has a disadvantage of slow control speed and no precise current control. Therefore, recently, the using of inverter type welding system is increasing. Conventional welding machine adopts several tens of switching devices connected in parallel to obtain a huge current of several thousands ampere with a short welding time. This paper analyzed a welding system consisting with 4 IGBT switches for a full-bridge inverter and conventional 60 [Hz] transformer. The simulation and experimental results show the validity of the proposed method.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.5 no.3
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• pp.206-215
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• 2005

In this paper, we propose a new design method of Genetic Algorithm Processor(GAP) and Evolvable Hardware(EHW). All sorts of creature evolve its structure or shape in order to adapt itself to environments. Evolutionary Computation based on the process of natural selection not only searches the quasi-optimal solution through the evolution process, but also changes the structure to get best results. On the other hand, Genetic Algorithm(GA) is good fur finding solutions of complex optimization problems. However, it has a major drawback, which is its slow execution speed when is implemented in software of a conventional computer. Parallel processing has been one approach to overcome the speed problem of GA. In a point of view of GA, long bit string length caused the system of GA to spend much time that clear up the problem. Evolvable Hardware refers to the automation of electronic circuit design through artificial evolution, and is currently increased with the interested topic in a research domain and an engineering methodology. The studies of EHW generally use the XC6200 of Xilinx. The structure of XC6200 can configure with gate unit. Each unit has connected up, down, right and left cell. But the products can't use because had sterilized. So this paper uses Vertex-E (XCV2000E). The cell of FPGA is made up of Configuration Logic Block (CLB) and can't reconfigure with gate unit. This paper uses Vertex-E is composed of the component as cell of XC6200 cell in VertexE

• Progress in Medical Physics
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• v.26 no.2
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• pp.99-105
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• 2015

The monitor chamber is a real time dosimetry device for the measurement and the control of radiation beam intensity of the linac system. The monitor chamber prototype was developed for monitoring and controlling radiation beam from the linac based radiation generator. The thin flexible printed circuit boards were used for electrodes of the two independent plane-parallel ionization chambers to minimize the attenuation of radiation beam. The dosimetric characteristics, saturation and linearity of the measured charge, were experimentally evaluated with the Co-60 gamma rays. The performance of the developed monitor chamber prototype was in an acceptable range and this study shows the possibility of the further development of the chamber with additional functions.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.6A
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• pp.379-385
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• 2003

In this paper, we propose a time constant control method for sieving local minimum problem of the multiuser detector using Hopfield neural network for synchronous multi-rate code division multiple access(CDMA) system in selective fading environments and its performance is compared with that of the parallel interference cancellation(PIC). We also assume that short scrambling codes of 256 chip length are used an uplink, suggest a simple correlation estimation algorithm and circuit complexity reduction method by using cyclostationarity property of short scrambling code.It is verified that multiuser detector using Hopfield neural network more efficiently cancels multiple access interference(MAI) and obtain better bit error rate and near-far resistant than conventional detector.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.5B
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• pp.469-479
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• 2009

The GEM frame is used a mean to deliver the variable length user data and consists of the header and the payload in the G-PON system. The HEC field of header protects contents of the header and is used to maintain GEM frame synchronization at the same time. When an LCDG (Loss of GEM Channel Delineation) occurs while receiving frames, the receiver have to discard corrupted frames until acquiring the synchronization again. Accordingly, high-speed synchronization method is required to minimize the frame loss. In this paper, we suggest not only a main state machine but a sub-state machine to reduce the frame loss when undetectable errors occurred in the GEM header. Also, we provide a more efficient and fast parallel structure to detect the starting point of the header. Finally, the proposed method is implemented with the FPGA and verified by the logic analyzer.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.50 no.5
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• pp.248-254
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• 2001

The traction power demand highly varies with time and train positions and the traction load is a large-capacity current at single phase converted from 3-phase power system. Subsequently, each phase current converted from 3-phase power system cannot be maintained in balance any longer and thus the traction load can bring about imbalance in three-phase voltage. Therefore, the exact assessment of voltage unbalance must be carried out preferentially as well as load forecast at stages of designing and planning for electric railway system. The evaluation of unbalance voltage in areas, such as electric railway depots should be a prerequisite with more accuracy. The conventional researches on voltage unbalance have dealt with connection schemes of the transformers used in ac AT-fed electric railroads system and induced formulas to briefly evaluate voltage unbalance in the system(3). These formulas are still being used widely due to their easy applicabilities on voltage unbalance evaluation. Meanwhile, they don't take into account detailed characteristics of ac AT-fed electric railroads system, being founded on some assumptions. Accordingly. accuracy still remains in question. This paper proposes a new method to more effectively estimate voltage unbalance index. In this method, numerous diverted circuits in electric railway depots are categorized in three components and each component is defined as a two-port network model. The equivalent circuit for the entire power supply system is also described into a two-port network model by making parallel and/or series connections of these components. Efficiency and accuracy in voltage unbalance calculation as well can be promoted by simplifying the circuits into two-port network models.