• Journal of the Korea Society of Computer and Information
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• v.11 no.2 s.40
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• pp.159-167
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• 2006

Lipreading has been suggested as one of the methods to improve the performance of speech recognition in noisy environment. However, existing methods are developed and implemented only in software. This paper suggests a hardware design for real-time lipreading. For real-time processing and feasible implementation, we decompose the lipreading system into three parts; image acquisition module, feature vector extraction module, and recognition module. Image acquisition module capture input image by using CMOS image sensor. The feature vector extraction module extracts feature vector from the input image by using parallel block matching algorithm. The parallel block matching algorithm is coded and simulated for FPGA circuit. Recognition module uses HMM based recognition algorithm. The recognition algorithm is coded and simulated by using DSP chip. The simulation results show that a real-time lipreading system can be implemented in hardware.

• Convergence Security Journal
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• v.17 no.2
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• pp.15-22
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• 2017

This paper presents new 8-bit implementation of AES. Most typical 8-bit AES designs are to reduce the circuit area by sacrificing its throughput. The presented AES architecture employs two separated S-box to perform round operation and key generation in parallel. From the simulation results of the proposed AES-128, the maximum critical path delay is 13.0ns. It can be operated in 77MHz and the throughput is 15.2 Mbps. Consequently, the throughput of the proposed AES has 1.54 times higher throughput than the other counterpart although the area increasement is limited in 1.17 times. The proposed AES design enables very low-area design without sacrificing its performance. Thereby, it can be suitable for the various IoT applications that need high speed communication.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.5 s.120
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• pp.486-495
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• 2007

In this paper, we present the design procedure of BPF(Band Pass Filter) for the suppression of LO(Local Oscillator) harmonics. The required suppression at given harmonics is the key issues in such a filter design, while the bandwidth and the suppression of the unwanted signals are more important in the conventional RF filter design. In LO filter design the bandwidth is used for the minimization of the insertion loss for the desired signal. In addition, we propose the novel tuning procedure based on Momentum to consider the unknown parasitic effects, which usually are not included in the circuit design step and results in undesirable and frustrating tuning after fabrication.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.22 no.5
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• pp.31-40
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• 2008

Recently, Contactless Power Supply(CPS) system has been broadly studied as a power supply system for Flat Panel Display(FPD) material transfer equipments. In mass production line, CPS systems on material transfer equipment are applied only in the straight sections with single operating vehicle. The formal CPS system was not adequate for curved section nor multiple operating vehicles. Therefore, this paper presents CPS system that consists of straight and curved section with multiple operation vehicles. The circuit topology of CPS system consists of full bridge configured serial-parallel resonant DC/DC converter. The control method for CPS system consists of duty control method on the primary power supply system to maintain constant resonant current. And the secondary power supply systems of multiple vehicles are self controled to maintain constant output voltage. Practically, the test result of dual vehicles on straight and curved section of material transfer equipments were satisfactory, and proved it's applicability on commercial use.

• Journal of Power Electronics
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• v.18 no.1
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• pp.70-80
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• 2018

A novel strategy based on a zero common mode voltage pulse-width modulation (ZCMV-PWM) technique and zero-sequence circulating current (ZSCC) feedback control is proposed in this study to eliminate ZSCCs between three-level neutral point clamped (NPC) voltage source inverters, with common AC and DC buses, that are operating in parallel. First, an equivalent model of ZSCC in a three-phase three-level NPC inverter paralleled system is developed. Second, on the basis of the analysis of the excitation source of ZSCCs, i.e., the difference in common mode voltages (CMVs) between paralleled inverters, the ZCMV-PWM method is presented to reduce CMVs, and a simple electric circuit is adopted to control ZSCCs and neutral point potential. Finally, simulation and experiment are conducted to illustrate effectiveness of the proposed strategy. Results show that ZSCCs between paralleled inverters can be eliminated effectively under steady and dynamic states. Moreover, the proposed strategy exhibits the advantage of not requiring carrier synchronization. It can be utilized in inverters with different types of filter.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.11
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• pp.1377-1383
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• 2019

Histogram equalization is the most frequently used algorithm for image enhancement. Its hardware implementation significantly outperforms in time its software version. The overall performance of FPGA-based implementation of histogram equalization can be improved by applying pipelining in the design and by exploiting the multipliers and a lot of SRAM blocks which are embedded in recent FPGAs. This work proposes how to implement a fast histogram equalization circuit for 8-bit gray level images. The proposed design contains a FIFO to perform equalization on an image while the histogram for next image is being calculated. Because of some overlap in time for histogram equalization, embedded multipliers and pipelined design, the proposed design can perform histogram equalization on a pixel nearly at a clock. And its dual parallel version outperforms in time almost two times over the original one.

• Journal of Advanced Navigation Technology
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• v.27 no.1
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• pp.63-70
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• 2023

In this work, a capacitive wireless power transfer (C-WPT) system is presented for wireless sensor system (WSS) applications in marine propulsion shafts. For a single Q factor on both sides of the coupling capacitor and reactive power removal from the circuit, a double-sided LCLC converter and transformers topology are designed to drive the rotary C-WPT system for WSS on the shaft. Parallel-connected parallel plate rotating capacitors with a capacitance of 170 pF are designed and implemented for the C-WPT system on a snow rotating shaft. In the experimental results, the C-WPT system achieved a transmission efficiency of 66.67% with 7.8 W output power at 3 mm distance and 1 MHz operating frequency. Therefore, it was proved that the fabricated C-WPT system can supply power to the WSS of the rotating shaft.

• Progress in Superconductivity and Cryogenics
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• v.8 no.2
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• pp.29-32
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• 2006

An advanced superconducting fault current limiter (SFCL) using $high-T_c$ superconducting (HTS) wire has been developed. The SFCL has a non-inductively wound magnet for reducing loss in normal state. Two types of non-inductively wound magnets, the solenoid type and the pancake type, were designed and manufactured by using Bi-2223 wire in this research. Short-circuit tests of the magnets were performed in sub-cooled $LN_2$ cooling system of 65 K. The magnets are thermally more stable and have a higher critical current in 65 K sub-cooled $LN_2$ cooling system than in 77 K saturated one. Because the resistivity of matrix at 65 K is lower than the resistivity at 77 K, the magnets generate a small resistance to reduce the fault current when the quench occurs. The magnets could limit the fault current to low current level with such a small resistance. The current limiting characteristic of the magnets was analyzed from the test result. The solenoid type was wound in parallel to make it non-inductive. The pancake type was also connected in parallel to be compared with the solenoid type in the same condition. The solenoid type was found to have a good thermal stability compared with the pancake type. It also had as large resistance as the pancake type to limit the fault current in sub-cooled $LN_2$ cooling system.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.93-96
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• 2008

This paper describes an efficient design of a multi-standard Viterbi decoder that supports multiple constraint lengths and code rates. The Viterbi decode. is parameterized for the code rates 1/2, 1/3 and constraint lengths 7, 9, thus it has four operation modes. In order to achieve low hardware complexity and low power, an efficient architecture based on hardware sharing techniques is devised. Also, the optimization of ACCS (Accumulate-Subtract) circuit for the one-point trace-back algorithm reduces its area by about 35% compared to the full parallel ACCS circuit. The parameterized Viterbi decoder core has 79,818 gates and 25,600 bits memory, and the estimated throughput is about 105 Mbps at 70 MHz clock frequency.

• Progress in Superconductivity and Cryogenics
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• v.6 no.3
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• pp.50-55
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• 2004

We fabricated and tested a resistive type superconducting fault current limiter (SFCL) of three-phase 6.6 $kV_{rms}/200 A_{rms}$ rating based on YBCO thin films grown on sapphire substrates with a diameter of 4 inches, Short circuit tests were carried out at a accredited test facility for single line-to- ground faults, phase-to-phase faults and three-phase faults, Each phase of the SFCL was composed of 8${\times}$6 elements connected in series and parallel respectively. Each element was designed to have the rated voltage of 600 $V_{rms}$. A NiCr shunt resistor of 23 Ω was connected to each element for simultaneous quenches. Firstly, single phase-to-ground fault tests were carried out. The SFCL successfully developed the impedance in the circuit within 0.12 msec after fault and controlled the fault current of 10 $kA_{rms} below 816 A_{peak}$ at the first half cycle. In addition, in case of phase-to-phase fault and three- phase fault test. simultaneous quenches among the SFCLs of the phases successfully accomplished. In conclusion. the SFCL showed excellent performance of current limitation upon fault and stable operation regardless of the amplitude of fault currents.