• The Transactions of the Korean Institute of Power Electronics
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• v.5 no.2
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• pp.170-175
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• 2000

A new quasi-parallel resonant DC link inverter is proposed for three phase soft switching application. By i inserting only one additional switch, the proposed inverter excludes both voltage stresses and restricted PWM p problems, which are demerits of the conventional resonant inverter. In this paper, the circuit operations are e explained in detail using the operational mode analysis of the proposed inverter and design methods of the r resonant components are suggest('x:l. Lastly, the applicable possibility of the proposed inverter is vel예fied t through the experimental results.

• The Transactions of the Korean Institute of Power Electronics
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• v.19 no.6
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• pp.549-556
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• 2014

This study proposes a parallel operation strategy for small wind turbine systems. A small wind turbine system consists of blade, permanent magnet synchronous generator, three-phase diode rectifier, DC/DC buck converter, and the battery load. This configuration has reliability, simple control algorithm, high efficiency, and low cost. In spite of these advantages, the system stops when unexpected failures occur. Possible failures can be divided into mechanical and electrical parts. The proposed strategy focuses on the failure of electrical parts, which is verified by numerical analysis through equivalent circuit and acquired general formula of small wind power generation systems. Simulation and experimental results prove its efficiency and usefulness.

• The Transactions of the Korean Institute of Power Electronics
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• v.23 no.1
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• pp.40-46
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• 2018

In this study, the output voltage balancing characteristics of parallel-input series-output (PISO) boost converter is analyzed. The PISO boost converter is derived by combining two basic boost converters. In comparison with the conventional three-level boost converter, the PISO boost converter can balance the output voltages under an unbalanced load condition without requiring additional circuit components and control strategy. A 2 kW prototype converter is built and tested to verify the output voltage balancing characteristics of the PISO boost converter.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.1
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• pp.45-48
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• 2010

An inter-pin skew compensation scheme is proposed, which minimizes the inter-pin skew of parallel interface induced by unequal trace length and loading of printed circuit board (PCB). The proposed scheme measures the inter-pin skew and compensates during power-up with simple hardware. The proposed scheme is applied to 3.2-Gb/s/pin DDR4 SDRAM and implemented in a 0.18 m CMOS process. The inter-pin skew is compensated in 324-cycles of 400-MHz clock and the skew is compensated to be less than 24-ps.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.66 no.3
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• pp.599-604
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• 2017

Nowadays reactance method is being used as a technique for fault location in parallel feeding AC traction power system. However, implementation of this method requires a large number of field tests(ground fault) which is a huge burden on the operators. This paper presents a new estimation technique using quadratic interpolation to reduce number of times for field test and improves the accuracy of fault location. To verify a new technique, we solve AT feeding circuit and model it using PSCAD/EMTDC. Finally this paper conducts a comparative analysis of usefulness between a new technique and real field data.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.41 no.6
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• pp.579-587
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• 1992

This paper is to study on the step-up DC-DC converter for power system which yields output characteristics of low voltage and high current, such as fuel cell generation system. DC-AC-DC scheme is suggested for high ratio of voltage conversion. Three phase MOSFET-SPWM inverter is adopted for intermediate AC conversion and inverter output frequency is chosen at 400[Hz] in order to reduce the size of magnetic circuit and DC filter. Since control strategy which combines voltage controller with current controller in parallel is used, good output performance is obtained both in steady state and in transient state like load variation, not only in single unit operation but also in parallel operation.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.54 no.12
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• pp.576-585
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• 2005

This paper deals with the electromagnetic field analysis of slotless brushless permanent magnet machines with three different magnetization patterns such as Halbach, parallel and radial magnetization. The magnetization modeling of Halbach, parallel and radial magnetization is performed analytically. And then, analytical solutions for open-circuit field distributions, armature reaction field distributions, flux linkages due to PMs and stator windings, torque, back-emf and inductance are derived in terms of magnetic vector potential and two-dimensional (2-d) polar coordinate systems. The analytical results are validated extensively by finite element (FE) analyses. The magnet volume required in order to produce identical flux density is compared with each magnetization. Finally, analytical solutions and derivation procedures of those presented in this paper can be applied to slotless and slotted brushless permanent magnet AC and DC machines.

• Proceedings of the KIEE Conference
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• 2005.07b
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• pp.1425-1427
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• 2005

In this paper, with loosely coupled transformer series-parallel resonant type DC/DC converter is analyzed. To get more efficient operating mode of the series-parallel resonant type DC/DC converter, theoretical analysis using normalized parameters are accepted. The proposed converter must be operated in Pulse Frequency Modulation(PFM) switching pattern for the Zero Voltage Switching(ZVS) operation. According to PFM control method, the output voltage of the proposed circuit can be controlled.

• Journal of the Korea Society of Computer and Information
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• v.6 no.3
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• pp.56-63
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• 2001

In this paper, The GF(216) multiplier using its subfields GF(24) is designed. This design can be used to construct a sequential logic multiplier using a bit-parallel multiplier for its subfield. A finite field serial multiplier using parallel multiplier of subfield takes a less time than serial multiplier and a smaller complexity than parallel multiplier. It has an advatageous feature. A feature between circuit complexity and delay time is compared and simulated using C language.

• ETRI Journal
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• v.44 no.2
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• pp.260-273
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• 2022

This study presents a novel multilayer structure of parallel coupled-line bandpass filtercentered at 2.42 GHz with a fractional bandwidth value of approximately 19.4%. The designed filter can suppress harmonics with an appropriate frequency response by incorporating different techniques based on the multilayer technique. A combination of different techniques such as radial microstrip stubs and defected ground structure (DGS) and defected microstrip structure techniques are employed to suppress harmonics up to 5f₀. These techniques are used in two layers to suppress up to 5f₀. In addition, in this study, the effects of different parameters, such as the width of slot-line DGS, the angle of diagonal line slots in the upper layer, and the air gap between the two layers on the filter performance, are investigated. To verify the correct circuit operation, the designed filter is implemented and tested. The measurement results of the proposed filter are compared with the simulation results.