• Proceedings of the KIPE Conference
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• 2002.07a
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• pp.24-28
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• 2002

In a motor driving, the current rate is directly related to the rate of a switching device and in cost reduction, the parallel switching operation is the alternatives because it has the smaller current rate through current division. There are many investigations for the parallel switching operations to equaling the current division. However it remains many problems for practical usage. The reason is that the switching characteristics are mainly relied on the different saturation voltage of each device etc. and these factors are not altered by a circuit designer. In order to compensate this problem, a proper resistance is experimently inserted to the switching device. But this method can not be the optimal solution. Therefore this paper proposes a new parallel operation which uses a parallel phase winding to remove the traditional effect of switching device such as saturation voltage according to the division of current. Also the reliable and stable driving is improved through experiments and the detailed principles.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.6 s.348
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• pp.38-46
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• 2006

A parallel analog Viterbi decoder which decodes PRML signal of DVD has been fabricated into a VLSI chip. The parallel analog Viterbi decoder implements the functions of the conventional digital Viterbi decoder utilizing the analog parallel processing circuit technology. In this paper, the analog parallel Viterbi decoding technology is applied for the PRML signal decoding of DVD. The benefits are low power consumption and less silicon consumption. The designed circuits are analysed and the test results of the fabricated chip are reported.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.1
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• pp.20-25
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• 2011

This paper analyzed the application of Superconducting Fault Current Limiter (SFCL) on 22.9 [kV] bus tie in a power distribution system. Commonly, the parallel operations of power main transformers offer a lot of merits. However, when a fault occurs in the parallel operation of power main transformer, the fault currents might exceed the interruption capacity of existing protective devices. To resolve this problem, thus, the SFCL has been studied as the fascinating device. In case that, Particularly, the SFCL could be installed to parallel operation of various power main transformers in power distribution system of the Korea Electric Power Corporation (KEPCO) on 22.9 [kV] bus tie, the effect of the resistance of SFCL could reduce the increased fault currents and meet the interruption capacity of existing protective devices by them. Therefore, we analyzed the effect of application and proposed the proper impedance of the R-type SFCL on 22.9 [kV] bus tie in a power distribution system using PSCAD/EMTDC.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.05a
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• pp.141-148
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• 2002

In a motor driving, the current rate is directly related to the rate of a switching device and in cost reduction, the parallel switching operation is the alternatives because it has the smaller current rate through current division. There are many investigations for the parallel switching operations to equaling the current division. However it remains many problems for practical usage. The reason is that the switching characteristics are mainly relied on the different saturation voltage of each device etc. and these factors are not altered by circuit designer. In order to compensate this problem, a proper resistance is experimently inserted to the switching device. But this method can not be the optimal solution. Therefore this paper proposes a new parallel operation which uses a parallel phase winding to remove the traditional effect of switching device such as saturation voltage according to the division of current. Also the reliable and stable driving is improved through experiments and the detailed principles.

• Journal of Chest Surgery
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• v.38 no.10 s.255
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• pp.661-668
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• 2005

Background: We have hypothesized that, if a low resistant gravity-flow membrane oxygenator is used, then the twin blood sacs of TPLS can be located at downstream of the membrane oxyenator, which may double the pulse rate at a given pump rate and increase the pump output. The purpose of this study was to determine the optimal configuration for the ECLS circuits by using the concept of pulse energy and pump output. Material and Method: Animals were randomly assigned to 2 groups in a total cardiopulmonary bypass model. In the serial group, a conventional membrane oxygenator was located between the twin blood sacs. In the parallel group, the twin blood sacs were placed downstream of the gravity-flow membrane oxygenator. Energy equivalent pressure (EEP) and pump output were collected at pump-setting rates of 30, 40, and 50 BPM. Result: At the given pump-setting rate, the pulse rate was doubled in the parallel group. Percent changes of mean arterial pressure to EEP were $13.0\pm1.7,\; 12.0\pm1.9\;and\;7.6\pm0.9\%$ in the parallel group, and $22.5\pm2.4,\; 23.2\pm1.9,\;and\;21.8\pm1.4\%$ in the serial group at 30, 40, and 50 BPM of pump-setting rates. Pump output was higher in the parallel circuit at 40 and 50 BPM of pump-setting rates $(3.1\pm0.2,\;3.7\pm0.2L/min\;vs.\;2.2\pm0.1\;and\;2.5\pm0.1L/min,\;respectively,\;p=0.01)$. Conclusion: Either parallel or serial circuit configuration of the ECLS generates effective pulsatility. As for the pump out, the parallel circuit configuration provides higher flow than the serial circuit configuration.

• The KIPS Transactions:PartA
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• v.17A no.3
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• pp.121-126
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• 2010

This paper proposes a low-power MOS current-mode logic circuit with the low voltage swing technology and the high-threshold sleep-transistor. The sleep-transistor is used to high-threshold voltage PMOS transistor to minimize the leakage current. The $16{\times}16$ bit parallel multiplier is designed by the proposed circuit structure. Comparing with the conventional MOS current-model logic circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/104. The proposed circuit is achieved to reduce the power consumption by 11.7% and the power-delay-product by 15.1% compared with the conventional MOS current-model logic circuit in the normal mode. This circuit is designed with Samsung $0.18\;{\mu}m$ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.1212-1213
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• 2011

PWM(pulse width modulation) rectifier has unit power factor and low harmonic distortion with high power conversion efficiency in entire loading range. These merits of PWM rectifier help the spread of DC distribution system. In addition, if multiple PWM rectifiers can be operated in parallel connection, maintenance process can be simple and reliability of power source can be advanced because of the hot swapping is available. The other way, the load unbalance among rectifiers can force a converter to stop by over current. The surge current by closed circuit composition between rectifiers can force switching devices damage. In this paper, some problems that can occur in case of parallel operation of PWM rectifiers and problem eliminating methods are considered.

• Proceedings of the KIEE Conference
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• 2003.11b
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• pp.79-82
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• 2003

This paper describes a new low-swing inverter for low power consumption. To reduce a power consumption, an output voltage swing is in the range from 0 to $V_{ref}-V_{TH}$, where $V_{ref}=V_{DD}-nV_{TH}$. This can be done by the inverter structure that allow a full swing or a swing on its input terminal without leakage current. Using this low-swing voltage technology, we propose a low-power $4\times4$ bit parallel multiplier. The proposed circuits are simulated with HSPICE under $0.35{\mu}m$ CMOS standard technology. Compare to the previous works, this circuit can reduce the power consumption rate of 11.2% and the power-delay product of 10.3%.

• Proceedings of the KSR Conference
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• 2007.05a
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• pp.858-863
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• 2007

With increase of load power the case it will not be able to supply the power which is necessary to the vehicle, it establishes dosage increase of main transformer of substation or power compensation equipment, and must supply the power which is necessary. But like this method the expense and the hour when it is considerable are necessary. As an alternative plan, if neighborhood substation can supply power through parallel feeding then it can supply power applying the equipment of existing. So we investigate the possibility of parallel feeding method between neighboring substations through measuring results of voltage phase difference and analysing feeding circuit,

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.864-865
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• 2008

This paper deals with d-q axis inductance measurements of IPMSM considering core loss at low speed. d-q axis inductance measurements generally are conducted at rated speed and parallel core loss model can be used to exclude core loss effects on inductances. Core loss is generally modeled parallel to input terminal of d-q axis equivalent circuit. Therefore, the effect of core loss on inductance calculation can be varied by core loss modeling. In this paper, d-q axis inductance is calculated parallel and series core loss modeling. Calculated inductances are compared to FEA results and it is concluded that series core loss modeling is more closed to FEA results at low speed.