• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1019-1022
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• 2003

This paper has proposed a 4- bit 20MHz Flash A/D converter design available analog signal processing and realized its intergrated circuit. The parallel comparison method A/D converter quantized analog signals swiftly using various converters. Also this theme has designed economic power dissipation circuit using a preamplifier of low volt & power CMOS comparator. Also the system was fabricated by Hynix 0.35um CMOS process.

• Proceedings of the KIPE Conference
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• 2002.07a
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• pp.253-256
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• 2002

This paper proposes the application of coreless PCB transformer to Half-Bridge (HB), Zero-voltage-Switched (ZVS) DC/DC converter for FPL lamp with electronic ballast in vehicle. The designed 5 coreless PCB transformers for ballast driving voltage are parallel-connected in primary windings and series-connected in secondary windings. Coreless PCB transformer is designed to have spiral winding in order to transfer higher energy. The computer simulations of the proposed power circuit show coreless PCB transformer to have good performance.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.12
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• pp.77-84
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• 1998

A voltage controlled chaotic circuit has been designed in integrated circuit and fabricated by using 0.8$\mu\textrm{m}$ single poly CMOS technology. The fabricated chaotic circuit consist of sample and hold circuits, op-amps, nonlinear function generator and two phase clock generator. The test results of the chaotic circuit show that periodic state, quasi-periodic state and chaotic state can be obtained according to the input control voltage with the ${\pm}$2.5V power supply and clock rate of 20kHz. In addition, two dimensional chaotic patterns have been observed by connecting this circuit in parallel or series

• Proceedings of the KIEE Conference
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• 2006.04b
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• pp.393-395
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• 2006

We investigated the operational characteristics of the hybrid-type superconducting fault current limiter (SFCL) according to the serial and parallel connections of secondary circuits. The hybrid-type SFCL consists of a transformer, which has a primary winding and several secondary windings with $YBa_2Cu_3O_7$ films connected in series and parallel. In order to increase the capacity of the SFCL, the serial connection between each current limiting unit is necessary. The hybrid-type SFCL with the serial connection in secondary circuits could show superior characteristics than those of the parallel connections in the current limiting and quench time. The resistances generated in the superconducting units were also lowered at the parallel connections. We confirmed that the parallel connection reduced the power burden of each superconducting unit under the same conditions because of the simultaneous quenching between superconducting units.

• Proceedings of the KIPE Conference
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• 2003.07a
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• pp.430-433
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• 2003

IGBTS are widely used for the industrial inverters in the mid power range at low voltage (440V$\~$660V) application. Advantageous features of the device are simple gate drive and high speed switching capability. Due to these advantages the application of IGBTS is enlarging into the high power application. However, to increase the power handling capacity at lower input voltage level, the current rating in each bridge arm must be enlarged. Therefore the parallel operation of IGBT devices is essentially needed. This paper describes the feasible parallel structures of the power circuit for the mid & the high power inverters and introduces the important design condition for the parallel operation of IGBT devices. To verify feasibility of the IGBT parallel operation, the feature of several IGBT devices (EUPEC, SEMIKRON's IGBT) are investigated and the power stacks are implemented and tested with these devices. The experimental results show the good characteristics for the parallel operation of IGBTS.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.5
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• pp.361-368
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• 2003

A new high-speed direct digital frequency synthesizer using a low power pipelined parallel accumulator is proposed. The proposed pipelined parallel accumulator uses both pipelining and paralleling techniques to increase speed and to reduce power consumption. The 2-pipelined 2-parallel accumulator only consumes 66% and 69% power of the 4-pipelined accumulator and the 4-parallel accumulator respectively with the same throughput. The proposed accumulator can achieve higher throughput with smaller area and less power consumption in lower clock frequency. All circuit simulations and implementations are based on a 0.35um CMOS process with VCC = 3.3V.

• Journal of Power Electronics
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• v.15 no.2
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• pp.327-337
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• 2015

This study discusses the design of a parallel-operated DC-DC single-ended primary-inductor converter (SEPIC) for low-voltage application and current sharing with a constant output voltage. A coupled inductor is used for parallel-connected SEPIC topology. Generally, two separate inductors require different ripple currents, but a coupled inductor has the advantage of using the same ripple current. Furthermore, tightly coupled inductors require only half of the ripple current that separate inductors use. In this proposed work, tightly coupled inductors are used. These produce an output that is more efficient than that from separate inductors. Two SEPICs are also connected in parallel using the coupled inductors with a single common controller. An analog control circuit is designed to generate pulse width modulation (PWM) signals and to fulfill the closed-loop control function. A stable output current-sharing strategy is proposed in this system. An experimental setup is developed for a 18.5 V, 60 W parallel SEPIC (PSEPIC) converter, and the results are verified. Results indicate that the PSEPIC provides good response for the variation of input voltage and sudden change in load.

• International journal of advanced smart convergence
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• v.4 no.1
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• pp.64-70
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• 2015

This paper proposes fluorescent electronic ballast with high power factor and low line input current harmonics. The system performance can be improved by a charged pump circuit. Details of design and circuit operation are described. The proposed electronic ballast is modified from single-stage half bridge class D electronic ballast by adding capacitor parallel with each power switch and setting the circuit parameter to operate under class DE inverter condition. By using this proposed method the DC bus voltage can be reduced around by 50% compare with conventional class D inverter circuit. Because the power switches are operated at zero voltage switching condition and low dv/dt of class DE switching. The experimental results show that the proper frequency of the prototype is around 50 kHz with input power factor of 0.982, $THD_i$ 10.2% at full load and efficiency of more than 90%.

• Proceedings of the KIPE Conference
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• 1997.07a
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• pp.417-422
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• 1997

This paper proposed that a AC-DC Converter topology of high power factor with soft switching mode operates with four chopper connecting a number of parallel circuit. To improve these, a large number of soft switching topologies included a resonant circuit have been proposed. And, some simulative results on computer is included to confirm the validity of the analytical results. The partial resonant circuit makes use of a inductor using step up and a condenser of loss-less snubber. The result is that the switching loss is very low and the efficiency of system is high. And the snubber condenser used in partial resonant circuit makes charging engergy regenerated at input power source for resonant operation. The proposed conversion system is deemed the most suitable for high power applications where the power switching devices are used.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2000.11a
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• pp.231-234
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• 2000

In this paper, we formed a transmitter and receiver by using three identical Chuas circuits and then formed wire and wireless transmission line from the channel which was between those three circuits. We proposed a secure communication method in which the desired information signal was synthesized with the chaos signal created in a Chuas circuit and sent to the transmitter through channel. Then the signal was demodulated receiver of Chuas circuit. The method we used to accomplish the secure communication was synthesizing the desired information with the chaos circuit by parallel connection in a wireless transmission line. After transmitting the synthesized signal to the wire and wireless transmission line, we confirmed the actuality of the secure communication by separating the information signal and the chaos signal in the receiver.