• 전력전자학회:학술대회논문집
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• 전력전자학회 2000년도 전력전자학술대회 논문집
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• pp.172-176
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• 2000

The paper presents the fault detection and isolation of two DC-DC converters parallel operation by ZCT method. Two experimental prototype converters were designed and implemented for evaluation of fault tolerant system. The experimental results show that fault detection and isolation circuit works very well.

• 전자공학회논문지C
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• 제36C권6호
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• pp.27-36
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• 1999

본 논문에서는 입출력간의 연관관계가 트리구조로 표현되는 DTG에 의한 고속병렬다치논리회로를 설계하는 알고리즘을 제안하였다. 본 논문에서는 Nakajima 등에 의해 제안된 알고리즘의 문제점을 도출한 후, 최적화된 분할연산회로설계를 위하여 트리구조에 기초를 둔 수학적인 해석의 개념을 소개한다. 본 논문에서 제안한 알고리즘은 Nakajima 등에 의해 제안된 알고리즘으로는 설계가 가능하지 않았던 임의의 절점을 갖는 DTG에 대해서도 회로를 설계할 수 있다는 장점이 있다. Nakajima 등에 의해 제안된 알고리즘과 본 논문에서 제한한 알고리즘을 회로설계의 관점에서 비교하여 본 논문의 알고리즘이 모든 경우의 DTG에서 보다 최적화 설계를 할 수 있음을 증명하였다. 그리고 예제를 통해 본 논문에서 제안한 알고리즘의 유용성을 증명해 보였다.

• 한국철도학회논문집
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• 제8권1호
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• pp.1-5
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• 2005

This paper has presented the parallel cyclic redundancy check (CRC) technique that performs CRC computation in parallel superior to the conventional CRC technique that processes data bits serially. Also, it has showed that the implemented parallel CRC circuit has been successfully applied to the inductively coupled passive RFTD system working at a frequency of 13.56㎒ in order to process the detection of logical faults more fast and the system has been verified experimentally. In comparison with previous works, the proposed RFID system using the parallel CRC technique has been shown to reduce the latency and increase the data processing rates about 15％ In the results. Therefore, it seems reasonable to conclude that the parallel CRC realization in the RFID system offers a means of maintaining the integrity of data in the high speed RFID system.

• ETRI Journal
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• 제32권4호
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• pp.555-565
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• 2010

Parallel simulation is an efficient way to cope with long runtimes and high computational requirements in simulations of modern complex integrated electronic circuits and systems. This paper presents an algorithm for parallel simulation based on parallelization in equation formulation and simultaneous calculation of matrix contributions for nonlinear analog elements. In addition, the paper describes the development of a grid interface for a parallel simulator that enables a designer to perform simulations on distant computer clusters. Performances of the developed parallel simulation algorithm are evaluated by simulation of a microelectromechanical system.

• 전력전자학회논문지
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• 제21권5호
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• pp.453-456
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• 2016

The major causes of electrical fire in low-voltage distribution lines are classified into short-circuit fault, overload fault, electric leakage, and electric contact failure. The special principal factor of the fire is electric arc or spark accompanied with such electric faults. This paper studies the development of an electric fire prevention system with detection and alarm of that in case of parallel arc fault occurrence in low-voltage distribution lines. The proposed system is designed on algorithm sensing the instantaneous voltage drop of line voltage at arc fault occurrence. The proposed detector has characteristics of high-speed operation responsibility and superior system reliability from composition using a large number of semiconductor devices. A new sensing control method that shows the detection of parallel arc fault is sensed to ripple voltage drop through a diode bridge full-wave rectifier at electrical accident occurrence. Some experimental tests of the proposed system also confirm the practicality and validity of the analytical results.

• 한국표면공학회지
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• 제55권4호
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• pp.231-235
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• 2022

As environmental pollution becomes more serious, the demand for electric vehicles (EVs) and lithium-ion batteries for electric vehicles is rapidly increasing worldwide. Accordingly, the amount of waste batteries is also increasing, and a technology for recycling and reusing them is required. In order to reuse a used battery, it is necessary to non-destructively diagnose the deterioration condition of the battery. Therefore, in this study, we investigate the diagnosis of degradation for parallel-connected lithium-ion battery cells through non-constructive electrochemical approach. As the number of parallel-connected cells increased, in addition to linear degradation, abrupt step-like degradation occurred, which is attributed to the predominant degradation of specific cells. In addition, it is confirmed that deteriorated cells among multiple cells can be distinguished through a simple measurement of open circuit voltage (OCV).

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2003년도 ICCAS
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• pp.960-964
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• 2003

In this paper, the CMOS integrated circuit technique for implementing current-mode maximum and minimum operations scheme is described. The maximum and minimum operations are incorporated into the same scheme with parallel processing. Using this scheme as the basic unit, an analog three-input maximum, median, and minimum circuit is designed. The performance of the proposed circuit shows a very sharp transfer characteristic and high accuracy. The proposed circuit achieves a high-speed operation, which is suitable for real-time systems. The PSPICE simulation results demonstrating the characteristic of the proposed circuit are included.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1997년도 하계학술대회 논문집 B
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• pp.533-535
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• 1997

Chua's circuit is a simple electronic network which exhibits a variety of bifurcation and attractors. The circuit consists of two capacitors, an inductor, a linear resistor, and a nonlinear resistor. In this paper we analyze a circuit obtained by replacing the parallel LC resonator in the Chua's circuit by lossless transmission line. By using the method of characteristics of this circuit we show that various periodic motions and chaotic motions can the attained according to parameter variations. From Chua's circuit with a lossless transmission line, a variety of chaotic attractors which are similar to those of the normal Chua's circuit are observed.

• 전자공학회논문지B
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• 제29B권10호
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• pp.10-18
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• 1992

This paper considers and implementation of the memory system which provides simultaneous access to pq image points of block(p$\times$q), horizontal vector(1$\times$pq)and/vertical vector(pq$\times$1) in 2-dimension image array, where p and q are design parameters. This memory system consists of an address calculation circuit, address routing circuit, data routing circuit, module selection circuit and m memory modules where m>qp. The address calculation circuit computes pq addresses in parallel by using the difference of addresses among image points. Extra module assignment circuit is not used by improving module selection circuit with routhing circuit. By using Verilog-XL logic simulator, we verify the correctness of the memory system and estimate the performance. The implemented system provides simultaneous access to 16 image points and is 6 times faster than conventional memory system.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 춘계학술대회 논문집
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• pp.3-3
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• 2010

The Characteristics of Digital Vterbi Decoder utilizing the analog parallel processing circuit technology is proposed. The Analog parallel structure of the viterbi decoder acted by a replacement of the conventional digital viterbi Decoder is progressing fastly. The proposed circuits design han, low distortion, high accuracy over the previous implementation and dynamic programming.