1 |
V. Litovski, D. Maksimović., and ZZ. Mrcarica, "Mixed-Signal Modeling with AleC++: Specific Features of the HDL," Simulation Practice and Theory, vol. 8, 2001, pp. 433-449.
DOI
ScienceOn
|
2 |
ZZ. Mrcarica et al., "Mechatronic Simulation Using Alecsis: Anatomy of the Simulator," Proc. Eurosim, 1995, pp. 651-656.
|
3 |
W. Gropp, E. Lusk, and A. Skjellum, Using MPI: Portable Parallel programming with the Message-Passing Interface, 2nd ed., Cambridge, Massachusetts: MIT Press, 1999.
|
4 |
W. Gropp, E. Lusk, and R. Thakur, Using MPI-2: Advanced Features of the Message-Passing Interface, Cambridge, Massachusetts: MIT Press, 1999.
|
5 |
S. Burke et al., "gLite3 User Guide," Available:http://edms.cern.ch/ file/722398/1.1/gLite-3-UserGuide.pdf, 2007
|
6 |
B. Andelkovic., V. Litovski, and P. Petkovic., "Implementation and Performance Analysis of Parallel Circuit Simulator on Beowulf Cluster," Proc. ETRAN Conf., 2007, (Proc. on CD, EL1.6.)
|
7 |
ZZ Mrcarica et al., "Describing Space-Continuous Models of Microelectromechanical Devices for Behavioural Simulation," Proc. EURO-DAC Euro. Design Automation Conf. with EUROVHDL, 1996, pp. 316-321.
|
8 |
ZZ Mrcarica et al., "Integrated Simulator for MEMS Using FEM Implementation in AHDL and Frontal Solver for Large-Sparse System of Equations," Proc. Design Test Microsyst., 1999, pp. 271-278.
|
9 |
"Intel TV Interview: Parallelizing Legacy EDA Applications," Available: http://www.cadence.com/Community/blogs/ii/archive/2009/12/16/intel-tv-interview-parallelizing-legacy-eda-applications.aspx
|
10 |
A. Sangiovanni-Vincentelli, C. Li-Kuan, and L. Chua, "An Efficient Heuristic Cluster Algorithm for Tearing Large-Scale Networks," IEEE Trans. Circuits Syst., vol. 24, no. 12, Dec. 1977, pp. 709-717.
DOI
|
11 |
T. Kage, F. Kawafuji, and J. Niitsuma, "A Circuit Partitioning Approach for Parallel Circuit Simulation," IEICE Trans. Fundamentals E77-A(3), 1994, pp. 461-466.
|
12 |
L.W. Nagel, SPICE 2, a Computer Program to Simulate Semiconductor Circuits, Memorandum ERL-M250, University of California, Berkley Press, 1975.
|
13 |
N. Fröhlich, V. Glöckel, and J. Fleischmann, "A New Partitioning Method for Parallel Simulation of VLSI Circuits on Transistor Level," Proc. Design, Automation Test in Europe, 2000, pp. 679-684.
|
14 |
Zoltan: Parallel Partitioning, Load Balancing and Data-Management Services, Available: http://www.cs.sandia.gov/Zoltan/
|
15 |
P. Frey et al., "SEAMS: Simulation Environment for VHDLAMS," Proc. Winter Simulation Conf., 1998, pp. 539-546.
|
16 |
M. Dimitrijević. et al., "Gridification and Parallelization of Electronic Circuit Simulator," Proc. INDEL, Conf. Ind. Electron., 2006, pp. 95-100.
|
17 |
M. Jakovljević. et al., "Transient Electro-Thermal Simulation of Microsystems with Space-Continuous Thermal Models in Analogue Behavioural Simulator," Microelectronics and Reliability, vol. 40, no. 3, 2000, pp. 507-516.
DOI
ScienceOn
|
18 |
A.R. Newton and A.L. Sangiovanni-Vincentelli, "Relaxation-Based Electrical Simulation," IEEE Trans. Electron. Devices, vol. 30, no. 9, Sept. 1983, pp. 1184-1207.
DOI
|
19 |
Z. Mrcarica, "Modelling of Microelectromechanical Devices and Simulation of Systems Using Hardware Description Language," (doctoral dissertation), Technical University Vienna, 1995.
|
20 |
V. Litovski and M. Zwolinski, VLSI Circuit Simulation Optimization, London: Chapman and Hall, 1997.
|
21 |
D. Glozic. et al., "Alecsis, the Simulator," Laboratory for Electronic Design Automation, Faculty of Electronic Engineering, University of Niss, Serbia, 1996, Available:http://leda.elfak.ni.ac.yu/ projects/Alecsis/alecsis.htm
|
22 |
T. Sterling, Beowulf Cluster Computing with Linux, MIT Press, Cambridge, Massachusetts, 2001.
|
23 |
I. Foster and C. Kesselmann, The Grid: Blueprint for a New Computing Infrastructure, San Francisco, CA: Morgan Kaufmann, 1999.
|
24 |
J.A.B. Fortes, R.J. Figueiredo, and M.S. Lundstrom, "Virtual Computing Infrastructures for Nanoelectronics Simulation," Proc. IEEE, vol. 93, no. 10, Oct. 2005, pp. 1839-1847.
DOI
|
25 |
Xyce Parallel Electronic Simulator home page, Available: http://www.cs.sandia.gov/xyce/
|
26 |
N. Fröhlich et al., "A New Approach for Parallel Simulation of VLSI-Circuits on a Transistor Level," IEEE Trans. Circuits Syst. I, vol. 45, no. 6, 1998, pp. 601-613.
DOI
ScienceOn
|
27 |
"Virtuoso Accelerated Parallel Simulator" Available: http://www.cadence.com/products/cic/accelerated_parallel/pages/default.aspx
|
28 |
D.E. Martin et al., "Analysis and Simulation of Mixed-Technology VLSI Systems," J. Parallel Distributed Computing, vol. 62, no. 3, 2002, pp. 468-493.
DOI
ScienceOn
|
29 |
Magma Touts First Parallel Fast Spice," EE Times, Mar. 2007, Available: http://www.eetasia.com/ART_8800456053_480100_NP_c6fee15f.HTM
|
30 |
"Enhanced HSPICE Revs up Circuit Simulation," EE Times, Mar. 2008, Available: http://www.eetasia.com/ART_8800510252_499495_NP_3ebd77e7.HTM
|
31 |
M. Wolf and E. Boman, "Parallel Processing '08: An Increasing Role for Combinatorial Methods in Large-Scale Parallel Simulations," June 2008, Available: http://www.siam.org/news/news. php?id=1378.
|