• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 춘계학술대회 논문집 전기기기 및 에너지변환시스템부문
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• pp.324-328
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• 2001

This paper presents parallel operation and control loop design of ZVT(Zero Voltage Transition) Full Bridge DC/DC Converter. At parallel operation of ZVT Full Bridge Converter, dynamic current shared inductor devides the same current of unit converter and ZVT circuit and aids to high efficiency in the system. Base on the modeling of ZVT. Full Bridge Converter, the control loop is designed using a simple two-pole, one-zero compensation circuit. To show the validity of the design procedures, the small signal analysis of the closed loop system and open loop system is carried out and the superiority of the dynamic characteristics is verified through the experiment with a 2kW, 50kHz prototype converter.

• 대한전기학회논문지:시스템및제어부문D
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• 제49권6호
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• pp.322-329
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• 2000

BIST(Built-in Self Test) has been considered as the most promising DFT(design-for-test) scheme for the present and future test strategy. The most serious problem in applying BIST(Built-in Self Test) into a large circuit is the excessive increase in test time. This paper is focused on this problem. We proposed a new BIST construction scheme which uses a parallel divide-and-conquer method. The circuit division is performed with respect to some internal nodes called test points. The test points are selected by considering the nodal connectivity of the circuit rather than the testability of each node. The test patterns are generated by only one linear feedback shift register(LFSR) and they are shared by all the divided circuits. Thus, the test for each divided circuit is performed in parallel. Test responses are collected from the test point as well as the primary outputs. Even though the divide-and-conquer scheme is used and test patterns are generated in one LFSR, the proposed scheme does not lose its pseudo-exhaustive property. We proposed a selection procedure to find the test points and it was implemented with C/C++ language. Several example circuits were applied to this procedure and the results showed that test time was reduced upto 1/2151 but the increase in the hardware overhead or the delay increase was not much high. Because the proposed scheme showed a tendency that the increasing rates in hardware overhead and delay overhead were less than that in test time reduction as the size of circuit increases, it is expected to be used efficiently for large circuits as VLSI and ULSI.

• 대한전기학회논문지
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• 제35권7호
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• pp.272-277
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• 1986

The system that follows to the resonance frequency of high frequency MOSFET inverter and varies according to the changes of load characteristics is proposed. Also we suggested a method how to select the resonant load type between series and parallel circuit for a given inverter type. It leads to the conclusion that in the case of high impedance loads, parallel resonant circuits are preferable, on the other hand, for low impedance loads, series resonant circuits are more preferable. For frequency tracking, a PLL circuit is used as main control element to detect the phase difference of current and voltage of load. The realized apparatus composed of control circuit and voltage type full-bridged MOSFET elements as main parts of inverter. A stable frequency follow-up characteristics are obtained for 1.2MHz, 1.5KW high frequency output and power is always supplied to the load with unity power factor.

• 한국조명전기설비학회지:조명전기설비
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• 제9권5호
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• pp.51-56
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• 1995

The transistors of single phase 3 level PWM Inverter compose output power transistors and neutral point clamping transistors, which are NPN transistors. Waveforms of driving signals for this are PWM waves for power transistors and period operating waves for neutral point clamping transistors, which signals made W-type modulation from rectangular and sine wave. The output power transistors operate at ON-time complementary and neutral point clamping transistors operate at OFF-time complementary respectively. Therefore, each transistors operate in half period at parallel. Characteristics of this inverter circuit is parallel switching method about series switching method of general inverter. As modulation of 3 level drive signals made from full-wave rectifier of sine wave and rectangular wave, which are level wave about 3 level of complementary transistor inverter. So, this circuit composed complementary operation inverter of NPN transistors only compare with PNP-NPN complementary inverter, which have high power 3 level inverter of complementary operation.

• 대한전자공학회논문지
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• 제25권4호
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• pp.366-371
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• 1988

A parallel-plate waveguide with a slit in its upper plate is analysed. An integral equation is formulated for the equivalent magnetic current and solved by the conventional moment method. Numerical results are presented for the magnetic current, reflection and transmission coefficients, a normalized radiated power in the slit, and equivalent circuit parameters. The equivalent circuit parameters are an useful quantities in the study of the E-plane coupled microstrip antennas.

• 한국소음진동공학회:학술대회논문집
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• 한국소음진동공학회 2002년도 춘계학술대회논문집
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• pp.202-207
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• 2002

This paper deals with a novel shunted actuator, which has a capability to suppress multi-mode vibration amplitudes by using a pair of piezoceramic patches. In order to describe the characteristic behaviors of shunted dampers connected with a series and a parallel resistor-negative capacitive branch circuit, the stiffness ratio and loss factor with respect to the non-dimensional frequency are considered. To obtain a guideline model of a piezo/beam system connected with a series and a parallel resistor-negative capacitor branch circuit, the governing equations of motion is derived through Hamiltons principle and a piezo sensor equation as well as a shunt damping matrix is developed. The theoretical analysis shows that the shunted actuator developed in this study can significantly reduce multiple-mode vibration amplitudes simultaneously over the whole structural frequency range.

• 한국항해항만학회:학술대회논문집
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• 한국항해항만학회 2006년도 Asia Navigation Conference
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• pp.79-84
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• 2006

A novel design of compact low-pass filter based on microstrip structure and its equivalent-circuit model are developed. The philosophy of the structure behind this novel microstrip low-pass filter is simple as it is composed of a pair of symmetrical parallel coupled-line and an open-stub. With this configuration, a finite attenuation pole near the stopband cutoff frequency is available and adjustable by simply tuning the circuit parameters. Furthermore, the rejection bandwidth of this type of low-pass filter can be extended. In order to validate the feasibility of the proposed design method, a low-pass filter based on a microstrip structure is designed, fabricated, and measured. Experimental results agree very well with the simulation and analytical results.

• 정보처리학회논문지A
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• 제18A권6호
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• pp.249-254
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• 2011

본 논문은 H.264 움직임 예측을 위해 휘도 성분과 색차 성분의 부화소를 생성하는 효율적인 부화소 보간기 회로 설계에 대해 기술한다. 제안된 구조를 기반으로 한 회로는 보간 연산을 위해 입력 데이터를 버퍼링하지 않고 수평, 수직, 대각선의 부화소 보간을 병렬로 처리한다. 휘도성분에 대한 1/2 화소, 1/4 화소 보간과 색차 성분에 대한 1/8 화소 보간을 동시에 처리하여 회로 성능을 더욱 개선하였다. 회로 크기를 줄이기 위해 본 논문에서는 병렬로 보간 연산을 처리하는데 필요한 모든 중간 데이터를 레지스터 대신 내부 SRAM에 저장하였다. 제안된 구조를 레지스터 전달 수준의 회로로 기술하였고, FPGA 보드에서 동작을 검증하였다. 또한 구현된 회로를 130nm CMOS 표준 셀 라이브러리를 이용하여 게이트 수준의 회로로 합성하였다. 합성된 회로의 크기는 20,674 게이트이고 최대 동작 주파수는 244MHz이다. 회로에 사용된 SPSRAM의 전체 크기는 3,232 비트이다. 구현된 회로는 논리 게이트와 SRAM을 포함하여 다른 논문에서 제안한 회로에 비해 크기가 작고 성능도 우수하다.

• 한국전자통신학회논문지
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• 제7권3호
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• pp.485-490
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• 2012

본 논문에서는 선박의 진동에 의하여 수명이 짧은 필라멘트를 사용하는 조명기구를 대체하기 위하여 선박용 LED 조명등 구동회로를 설계 및 구현하였다. 구동회로는 부피를 줄이고 비용을 절감하기 위하여 변압기가 없는 스위칭 회로로 설계되었다. 스위칭 회로는 입력 교류전압 220 V에 PWM 제어를 함으로써 안정적으로 LED를 구동할 수 있도록 설계하였다. 스위칭 회로의 펄스성 전류에 대하여 Valley-fill 방식의 역률 보상회로를 채용함으로써 역률를 개선하였다. 장기간 운항하는 선박에서의 조명등 교체 주기를 줄여 관리를 효율적으로 할 수 있도록 직병렬 배열로 LED 모듈 회로를 설계하여 LED의 일부가 손상되더라도 LED 모듈이 조명등 기능을 할 수 있도록 하였다. 개발한 구동회로를 포함한 조명기구는 전력소모와 역률이 각각 39 W, 0.925 로 선박 조명에 적합함을 확인하였다.

• 조명전기설비학회논문지
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• 제19권8호
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• pp.116-121
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• 2005

전류모드 아날로그 회로를 이용하여 FIR(Finite Impulse Response) 필터를 설계하는 경우에 tap coefficient와 전류모드 FFT(Fast Fourier Transform) LSI의 회전인자(twiddle factor)를 실현시키기 위해서는 높은 정밀도를 갖는 전류 감쇠 회로가 필요하게 된다. 본 논문은 전류 모드 신호처리 기술에서 전류감쇠 회로의 감쇠 정밀도를 향상시킬 수 있는 기술을 소개하고자한다. 먼저 게이트 길이 비율을 조정하는(gate-ratioed) Current Mirror 회로를 사용하는 기존의 전류 감쇠 조정회로에 있어서의 DC offset 전류 에러에 대하여 분석하였으며, 다음으로 DC offset 전류 에러를 제거할 수 있는 전류감쇠 회로를 제안하였다. 회로 구성은 입력 전류를 1/N로 감쇠시킬 수 있도록 N개의 Current Mirror를 병렬로 연결하는 기본 구성을 하였으며, Kirchhoff 전류 법칙에 근거하여, 전류 감쇠가 결정되도록 설계하였다. 또한 Current Mirror 회로에서, 정전류원의 사용을 줄일 수 있는 회로설계를 제안하였다. 제안된 전류 감쇠 회로에서 정밀도는 Current Mirror의 ac 이득 에러에 의하여 제한되며 High Swing Current Mirror를 기본 Current Mirror로 사용한 경우에, 최대 정밀도는 이론상 입력 전류의 -80[dB]까지 실현가능하다.