• 제어로봇시스템학회:학술대회논문집
• /
• 제어로봇시스템학회 2005년도 ICCAS
• /
• pp.792-793
• /
• 2005

Circuit testing process is very important in IC Manufacturing there are two ways in research for circuit testing improvement. These are ATPG Tool Design and Test simulation application. We are interested in how to use parallel technique such as one-side communication, parallel IO and dynamic Process with data partition for circuit testing improvement and we use one-side communication technique in this paper. The parallel ATPG Tool can reduce the test pattern sets of the circuit that is designed in laboratory for make sure that the fault is not occur. After that, we use result for parallel circuit test simulation to find fault between designed circuit and tested circuit. From the experiment, We use less execution time than non-parallel Process. And we can set more parameter for less test size. Previous experiment we can't do it because some parameter will affect much waste time. But in the research, if we use the best ATPG Tool can optimize to least test sets and parallel circuit testing application will not work. Because there are too little test set for circuit testing application. In this paper we use a standard sequential circuit of ISCAS89.

• 대한전기학회논문지:시스템및제어부문D
• /
• 제54권8호
• /
• pp.475-481
• /
• 2005

In the existing ICT technique, the mounted electronic devices on the printed circuit board are tested whether the devices are good or not by comparing and measuring the value of the devices after separating the devices to be tested from around it based on the guarding method. But, in case that resistance, inductor and capacitor are configured as a parallel circuit on the circuit pattern, values for each device can not be measured because the total impedance value of the parallel circuit is measured. Accordingly, it is impossible to test whether the parallel circuit is good or not in case that the measured impedance value is within the tolerance error. Also, it is difficult to identify that which device among R, L and C of the parallel circuit is bad in case that the measured impedance value is out of the tolerance error. Accordingly, this paper proposes a test method which can enhance the quality and productivity by separating and measuring accurately R, L and C components from the RLC parallel circuits on the device-mounted printed circuit board. First, the RLC parallel circuit to be test is separated electrically from around it using three-terminal guarding technique. And then R, L and C values are computed based on the total impedance values and phase angles between voltage and current of the parallel circuit measured from two AC input signals with other frequency, Finally, the availability and accuracy of the proposed test method is verified by reviewing the simulation results.

• 한국전기전자재료학회논문지
• /
• 제18권9호
• /
• pp.863-869
• /
• 2005

We investigated quench characteristics of superconducting elements connected in series and parallel each other. The serial and parallel connections of superconducting elements causes a difficulty in simultaneous quench due to slight difference between their critical current densities. In other to induce simultaneous quench, we fabricated four type circuits; serially connected circuit before parallel connection, the circuit connected in parallel before serial connection, serially connected circuit before parallel connection with reactors, the circuit connected in Parallel before serial connection with reactors. We confirmed that the simultaneous quenches occurred in serial and parallel connections of superconducting elements using reactors. In addition, the power burden of superconducting elements was smaller than those of serial and parallel connections of superconducting elements without reactors.

• 설비공학논문집
• /
• 제22권5호
• /
• pp.259-267
• /
• 2010

An experiment has been performed in order to investigate the characteristics of multiple thermoelectric modules (TEMs) with electrical circuits. The open circuit voltage of TEM connected parallel circuit is equal to the sum of individual TEMs. In contrast, the open circuit voltage is equal to the average of that individual TEM for a series circuit. The power output and conversion efficiency of TEM for both parallel and series circuits increase as the operating temperature conditions for individual TEMs becomes identical. Comparing parallel with series circuits, the power generation performance is more excellent for series circuit than parallel circuit. This result is attributed to the power loss from the TEM with better power generation performance.

• 전력전자학회:학술대회논문집
• /
• 전력전자학회 1996년도 창립기념 전력전자학술발표회 논문집
• /
• pp.56-59
• /
• 1996

In this paper, we developed a micro-stepping drive circuit of step motor and proposed software algorithm for parallel operation of step motors drived by micro-stepping circuit. Also, we implemented a parallel operation controller with a 16-bit micro-controller.

• 한국음향학회지
• /
• 제38권2호
• /
• pp.222-230
• /
• 2019

본 논문에서는 유체의 와류 현상을 이용한 에너지 하베스팅 회로의 전력을 분석하였다. 와류를 전기 에너지로 바꾸기 위한 소자로 PVDF(Polyvinylidene fluoride) 압전 센서를 사용하였으며, 전력 분석을 위해 잘 알려진 브리지 다이오드 정류 회로와 전력 변환 효율을 향상시키기 위해 다이오드 정류회로 입력단에 병렬 동기 스위치 회로를 접목한 P-SSHI(Parallel Synchronized Switch Harvesting on Inductor) 정류 회로를 사용하였다. 다이오드 및 P-SSHI 정류 회로의 출력 전력은 이론을 통해 분석하였고 실험을 통해 검증하였다. 공기에 의한 와류를 이용한 실험을 통해 P-SSHI 정류 회로의 전력효율이 69 % 증가됨을 확인하였다. 또한 수확된 와류 에너지를 슈퍼 커패시터에 저장하는 회로를 구현하여 2차 전지로써 활용이 가능함을 확인하였다.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2007년도 추계학술대회 논문집
• /
• pp.478-479
• /
• 2007

Many electrical fires are occurred by leakage currents and sparks generated by a short circuit. Earth leakage circuit breakers (ELCBs) should be tripped at the moment of the faults mentioned above. In this paper, we described the tripping characteristics of ELCBs against parallel arcing faults. A diesel engine generator with the capacity of 375 kVA source was adopted to provide enough large current when a parallel arcing occurred. The experimental results showed that most ELCBs we experimented were not tripped against short-duration pulse currents produced by parallel arcing because the ELCBs are designed to be tripped by a large current with long duration similar to power frequency.

• 한국태양에너지학회:학술대회논문집
• /
• 한국태양에너지학회 2008년도 춘계학술발표대회 논문집
• /
• pp.241-246
• /
• 2008

In this paper, we analyze the I-V curve and hot-spot phenomenon caused by solar cells' serial and parallel connected circuit. The mis-match loss of parallel interconnection with low Isc string decrease lower than serially interconnected one and temperature caused by hot-spot does. Also, mis-match loss of parallel interconnection with low Voc string increase more than serially interconnected one. The string having low Voc happened hot-spot phenomenon when open circuit. The bad solar cell in string gives revere bias to good solar cell and make hot-spot phenomenon. If we consider the mis-match loss, when designing PV module and array. the efficiency of PV system might increase.

• 한국전자파학회논문지
• /
• 제19권7호
• /
• pp.761-770
• /
• 2008

임피던스 인버터 및 어드미턴스 인버터는 마이크로파 여파기 설계에 자주 사용되는 개념적인 소자이다. 본 논문에서는 일반적 무 손실 2-포트 회로의 인버터를 사용한 등가회로를 제시하였다 이 방법은 기존의 방법과 달리 무손실 2-포트 회로의 z- 또는 y-파라미터를 알 경우, 이를 이용하여 용이하게 나타낼 수 있다. 이 방법을 평행 결합 선로(parallel coupled line) 및 비평행 결한 선로(anti-parallel coupled line)에 적용하고, 기존의 등가회로에 대하여 비교 검토하였다. 또한, 마이크로스트립 평행 결합 선로 여파기는 설계된 여파기에 대해 주파수 응답의 왜곡을 발생시키게 되는데, 이를 보상하기 위하여 알려진 기존 결과들과 본 논문의 유도 결과를 비교 검토하였다. 평행 결합 선로 여파기 설계시 제시된 등가회로는 기존 등가회로와의 차이로 여파기 설계에 특이성을 보이게 된다. 본 논문에서는 제시된 등가회로에 대하여 설계 방법을 제시하고, 기존의 연구 결과와 비교하여 제시된 방법이 보다 정확한 결과를 주는 것을 보였다.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2005년도 심포지엄 논문집 정보 및 제어부문
• /
• pp.148-151
• /
• 2005

This paper proposes a high speed interface using redundant multi-valued logic for high speed communication ICs. This circuit is composed of encoding circuit that serial binary data are received and converted into parallel redundant multi-valued data, and decoding circuit that convert redundant multi-valued data to parallel binary data. Because of the multi-valued data conversion, this circuit makes it possible to achieve higher operating speeds than that of a conventional binary logic. Using this logic, a 1:4 demultiplexer (DEMUX, serial-parallel converter) IC was designed using a 0.35${\mu}m$ standard CMOS Process. Proposed demultiplexer is achieved an operating speed of 3Gb/s with a supply voltage of 3.3V and with power consumption of 48mW. Designed circuit is limited by maximum operating frequency of process. Therefore, this circuit is to achieve CMOS communication ICs with an operating speed greater than 3Gb/s in submicron process of high of operating frequency.