• Journal of Power Electronics
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• v.11 no.6
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• pp.870-879
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• 2011

Regulated peak power tracking (RPPT) systems such as the series structure and the series-parallel structures are commonly used in satellite space power systems. However, these structures process the solar array power or the battery power to the load through two cascaded regulators during one orbit cycle, which reduces the energy transfer efficiency. Also the battery charging time is increased due to placement of converter between the battery and the solar array. In this paper a parallel structure has been proposed which can improve the energy transfer efficiency and the battery charging time for satellite space power RPPT systems. An analogue controller is used to control all of the required functions, such as load voltage regulation and solar array stabilization with maximum power point tracking (MPPT). In order to compare the system efficiency and the battery charging efficiency of the proposed structure with those of a series (conventional) structure and a simplified series-parallel structure, simulations are performed and the results are analyzed using a loss analysis model. The proposed structure charges the battery more quickly when compared to the other two structures. Also the efficiency of the proposed structure has been improved under different modes of solar array operation when compared with the other two structures. To verify the system, experiments are carried out under different modes of solar array operation, including PPT charge, battery discharge, and eclipse and trickle charge.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.5
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• pp.87-94
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• 2002

In this paper an asynchronous away multiplier with a parallel array structure is introduced. This parallel array structure is used to make the computation time faster with a lower Power consumption. Asymmetric parallel away structure is used to minimize the average computation time in an asynchronous multiplier. Simulation shows that this structure reduces the time needed for computation by 55% as compared to conventional booth encoding array structures and that the multiplier with the proposed away structure shows a reduction of 40% in the computational time with a relatively lower power consumption.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.141-144
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• 2000

In this paper, a new parallel array structure for the asynchronous array multiplier is introduced. This structure is designed for a data dependent asynchronous multiplier to reduces power which is wasted in conventional array structure. Simulation shows that this structure saves 30％ of power and 55％ of computation time comparing to conventional booth encoded array multiplier.

• International Journal of Contents
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• v.9 no.1
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• pp.33-37
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• 2013

BCH code is one of the most widely used error correcting code for the detection and correction of random errors in the modern digital communication systems. The conventional BCH encoder that is operated in bit-serial manner cannot adequate with the recent high speed appliances. Therefore, parallel encoding algorithms are always a necessity. In this paper, we introduced a new systolic array type BCH parallel encoder. To study the area and speed, several parallel factors of the systolic array encoder is compared. Furthermore, to prove the efficiency of the proposed algorithm using tree-type structure, the throughput and the area overhead was compared with its counterparts also. The proposed BCH encoder has a great flexibility in parallelization and the speed was increased by 40% than the original one. The results were implemented on synthesis and simulation on FPGA using VHDL.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.269-272
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• 2001

In this paper we proposed the format converter design and implementation for real time image processing. This design method is based on realized the large processor-per-pixel array by integrated circuit technology in which this two types of integrated structure is can be classify associative parallel processor and parallel process with DRAM cell. Layout pitch of one-bit-wide logic is identical memory cell pitch to array high density PEs in integrate structure. This format converter design has control path implementation efficiently, and can be utilized the high technology without complicated controller hardware. Sequence of array instruction are generated by host computer before process start, and instructions are saved on unit controller. Host computer is executed the pixel-parallel operation starting at saved instructions after processing start

• Journal of Electrical Engineering and information Science
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• v.1 no.1
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• pp.98-107
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• 1996

In this paper, we propose a scheme that maps the time-delay neural network (TDNN) into the neurocomputer called EMIND-II which has the wavefront toroidal mesh-array structure. This neurocomputer is scalable, consists of many timeshared virtual neurons, is equipped with programmable on-chip learning, and is versatile for building many types of neural networks. Also we define the programming model of this array and derive the parallel algorithms about TDNN for the proposed neurocomputer EMIND-II. In addition, the computational complexities for the parallel and serial algorithms are compared. Finally, we introduce an application of this neurocomputer to word recognition.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.10
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• pp.36-42
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• 1997

In the whole world, the research about the VLSI implementation of motion estimation algorithm is progressed to actively full (brute force) search algorithm research with the development of systolic array possible to parallel and pipeline processing. But, because of processing time's limit in a field to handle a huge data quantily such as a high definition television, many problems are happened to full search algorithm. In the paper, as a fast processing to using parallel scheme for the serial input image data, motion estimator of systolic array structure verifying that processing time is improved in contrast to the conventional full search algorithm.

• Journal of the Korean Solar Energy Society
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• v.36 no.4
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• pp.57-65
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• 2016

Domestic photovoltaic system for roof-top is installed towards the south at an angle of 20 to 35 degrees and the shape of PV array is divided into two kinds; a plane shape and a curved shape. This paper aims to understand an actual condition of PV facility and strengths and weaknesses of support structure production and installation and to consider the best PV surface shape by analyzing theoretical logics of these two surface shapes and architectural perspective-based realistic case studies. This study targeted 98 facilities including common houses, public institutions and education institutions. In common houses, all of 59 PV facilities have a plane surface. In public institutions, 7 of 15 PV facilities have a curved array surface and 8 PV facilities have a plane surface. In education institutions, also, 14 of 24 PV facilities have a plane array surface and 10 PV facilities have a curved surface. Most of 98 facilities have a flat roof supporting shape. However, it was found that the curved shape wasn't positive for PV generation due to the change of radial density and it was at least 10 % more expensive to produce its structure. Also, domestic general large single-plate PV facilities have problems of harmony with buildings and wind load. Therefore, it is considered that for fixed-type roof-top PV, a plane PV array shape is good for optimum generation and economic efficiency and a parallel array structure on the roof surface is favorable to wind load and snow load without being a hindrance to the building facade.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.7
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• pp.1-13
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• 1993

In this paper, the problems of the conventional special-purpose array processor such as the deficiency of flexibility have been investigated. Then, a new modified methodology has been suggested and applied to obtain the common solution of the three typical App algorithms like SP(Shortest Path), TC(Transitive Closure), and MST(Minimun Spanning Tree) among the various APP algorithms using the similar method to obtain the solution. In the newly proposed APP parallel algorithm, real-time Processing is possible, without the structure enhancement and the functional restriction. In addition, we design 2-demensional bit-parallel low-triangular systolic array processor and the 1-PE in detail. For its evaluation, we consider its computational complexity according to bit-processing method and describe relationship of total chip size and execution time. Therefore, the proposed processor obtains, on which a large data inputs in real-time, 3n-4 execution time which is optimal o(n) time complexity, o(n$^{2}$) space complexity which is the number of total gate and pipeline period rate is one.

• Journal of Magnetics
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• v.22 no.2
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• pp.238-243
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• 2017

In this research, we report the preliminary results of an insertional type parallel transmission (pTx) array that has 7-elements that are placed in the space above a patient table as a transmit (Tx) coil to give an RF transmission ($B_1{^+}$) field for the body object of a 3 Tesla (T) MRI system. In previous research, we have tried to compare the performances of different coil elements and array geometries for a pTx body image. Based on these results, we attempt to obtain a human image with the proposed pTx array. Through the simulation and experimental results, we introduce a possible structure of multi-channel Tx array and verify the utility of a multi-channel Tx body image using $B_1{^+}$ shimming. The insertional pTx array, combined with a receiver (Rx) array coil, provides an enhanced $B_1{^+}$ field homogeneity in a large ROI image as a result of $B_1{^+}$ shimming applied over the full body size object. Through this research, we hope to determine the usefulness of the proposed insertional type RF coil combination for 3 T body imaging.