Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Array Structure for Asynchronous Low Power Multiplier

저전력 비동기 곱셈기를 위한 배열 구조

  • 박찬호 (광주과학기술원 정보통신공학과 병행시스템연구실) ;
  • 최병수 (광주과학기술원 정보통신공학과 병행시스템연구실) ;
  • 이동익 (광주과학기술원 정보통신공학과 병행시스템연구실)
  • Published : 2000.06.01
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Abstract

In this paper, a new parallel array structure for the asynchronous array multiplier is introduced. This structure is designed for a data dependent asynchronous multiplier to reduces power which is wasted in conventional array structure. Simulation shows that this structure saves 30％ of power and 55％ of computation time comparing to conventional booth encoded array multiplier.

Keywords