• Journal of Sensor Science and Technology
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• v.24 no.3
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• pp.188-193
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• 2015

This paper presents a new byte-wise BCH (4122, 4096, 2) decoder, which treats byte-wise parallel operations so as to enhance its throughput. In particular, we evaluate the parallel processing technique for the most time-consuming components such as syndrome generator and Chien search owing to the iterative operations. Even though a syndrome generator is based on the conventional LFSR architecture, it allows eight consecutive bit inputs in parallel and it treats them in a cycle. Thus, it can reduce the number of cycles that are needed. In addition, a Chien search eliminates the redundant operations to reduce the hardware complexity. The proposed BCH decoder is implemented with VHDL and it is verified using a Xilinx FPGA. From the simulation results, the proposed BCH decoder can enhance the throughput as 43% and it can reduce the hardware complexity as 67% compared to its counterpart employing parallel processing architecture.

• The Journal of the Korea Contents Association
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• v.16 no.3
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• pp.91-101
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• 2016

This paper presents the design of new parallel BCH decoder for MLC NAND flash memory. The proposed decoder supports the multi-byte parallel operations to enhance its throughput. In addition, it employs a LFSR-based parallel syndrome generator for compact hardware design. The proposed BCH decoder is synthesized with hardware description language, VHDL and it is verified using Xilinx FPGA board. From the simulation results, the proposed BCH decoder enhances the throughput by 2.4 times than its predecessor employing byte-wise parallel operation. Compared to the other counterpart employing a GFM-based parallel syndrome generator, the proposed BCH decoder requires the same number of cycles to complete the given works but the circuit size is reduced to less than one-third.

• The Journal of the Korea institute of electronic communication sciences
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• v.13 no.2
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• pp.333-340
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• 2018

This paper introduces a BCH code decoder using parallel CRC(: Cyclic Redundancy Check) generation. Using a conventional parallel syndrome generator with a LFSR(: Linear Feedback Shift Register), it takes up a lot of space for a short code. The proposed decoder uses the parallel CRC method that is widely used to compute the checksum. This scheme optimizes the a syndrome generator in the decoder by eliminating redundant xor operation compared with the parallel LFSR and thus minimizes chip area and propagation delay. In simulation results, the proposed decoder has accomplished propagation delay reduction of 2.01 ns as compared to the conventional scheme. The proposed decoder has been designed and synthesized in $0.35-{\mu}m$ CMOS process.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.6C
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• pp.619-625
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• 2009

This paper proposes a parallel architecture of a Parity Checksum Generator adopted for packet synchronization and error detection in the ITU-T Recommendation J.83 Annex B. The proposed parallel processing architecture removes a performance bottleneck occurred in a conventional serial processing architecture, leading to significant decrease in processing time for generating a Parity Checksum. The implementation results show that the proposed parallel processing architecture reduces the processing time by 83.1% at the expense of 16% area increase.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.1
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• pp.83-91
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• 1993

In the digital transmission system, cyclic redundancy check(CRC) code is widely used because it is easy to be implemented and has good performance in error detection. CRC code generator consists of several shift registers and modulo 2 adders. After manipulation of input data stream in the encoder, the remaining value of shift registers becomes CRC code. At the receiving side, error can be detected and corrected by CRC codes immediately transmitted after data stream. But, in the high speed system such as an A TM switch, it is difficult to implement the serial CRC encoder because of speed limitation of available semiconductor devices. In this paper, we propose the efficient parallel CRC encoder and syndrome calculator to solve the speed problem in implementing these functions using the existing semiconductor technology.

• Journal of Acupuncture Research
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• v.36 no.2
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• pp.100-106
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• 2019

Background: In Korean medicine, carpal tunnel syndrome is treated by stimulating the acupoints around the wrist. Although a deep understanding of anatomy and guidance is needed to stimulate these acupoints to avoid undesirable side-effects, currently there are no published guidelines for acupotomy treatment. The aim of this study is to evaluate the effectiveness and safety of fluoroscopy-guided acupotomy compared with conventional acupotomy treatment. Methods: This is a randomized, patient-assessor, patient blind, parallel clinical trial. A total of 30 patients will be enrolled at Wonkwang University Gwangju Hospital, and will be allocated to either an experimental group or a control group. The experimental group will be treated using fluoroscopy-guided acupotomy and the control group will be treated using the conventional acupotomy method. Results: The primary outcome measure will be identification of a cross-section area of the median nerve measured by ultrasonography, and the secondary outcome measure will be the alleviation of pain measured by the Visual Analogue Scale, improvement in the Nerve Conduction Study, Tinel test, Phalen's test, EuroQol 5-dimension scale, and Boston Carpal Tunnel Questionnaire score. Safety components will be measured by monitoring vital signs, electrocardiographs, blood tests, general chemical tests, urine tests and pregnancy tests. In addition, observations for adverse effects will be performed during the trial. Conclusion: This study will provide a more effective, and less harmful way of treating carpal tunnel syndrome compared with conventional acupotomy. Fluoroscopy-guided acupotomy will help practitioners to be accurate in direction and depth of the needle for treating carpal tunnel syndrome.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.465-472
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• 2013

This paper presents a low-complexity triple-error-correcting parallel Bose-Chaudhuri-Hocquenghem (BCH) decoder architecture and its efficient design techniques. A novel modified step-by-step (m-SBS) decoding algorithm, which significantly reduces computational complexity, is proposed for the parallel BCH decoder. In addition, a determinant calculator and a error locator are proposed to reduce hardware complexity. Specifically, a sharing syndrome factor calculator and a self-error detection scheme are proposed. The multi-channel multi-parallel BCH decoder using the proposed m-SBS algorithm and design techniques have considerably less hardware complexity and latency than those using a conventional algorithms. For a 16-channel 4-parallel (1020, 990) BCH decoder over GF($2^{12}$), the proposed design can lead to a reduction in complexity of at least 23 % compared to conventional architecttures.

• Clinical and Experimental Pediatrics
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• v.49 no.7
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• pp.710-717
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• 2006

Type 2 diabetes mellitus in children and adolescents has been increasing for last 10 years. The increase in frequency of type 2 diabetes appears to parallel the increase in prevalence and severity of obesity in children and adolescents. The metabolic syndrome, cluster of potent risk factors for atherosclerotic cardiovascular disease and type 2 diabetes, consists of insulin resistance, obesity, hypertension and hyperlipidemia. The atherosclerotic cardiovascular disease are rarely seen in the young, but the pathologic processes and risk factors are associated its development have been shown to begin during childhood. In pediatrician it is important to recognize early and treat aggressively for prevention of future cardiovascular disease in children and adolescents with metabolic syndrome.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.7
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• pp.909-915
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• 1999

In this paper, we propose an efficient VLSI architecture of Reed-Solomon(RS) decoder. To improve the speed. we develope an architecture featuring parallel and pipelined processing. To implement the parallel and pipelined processing architecture, we analyze the RS decoding algorithm and the honor's algorithm for parallel processing and we also modified the Euclid's algorithm to apply the efficient parallel structure in RS decoder. To show the proposed architecture, the performance of the proposed RS decoder is compared to Shao's and we obtain the 10 % efficiency in area and three times faster in speed when it's compared to Shao's time domain decoder. In addition, we implemented the proposed RS decoder with Altera FPGA Flex10K-50.

• Pediatric Gastroenterology, Hepatology & Nutrition
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• v.23 no.3
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• pp.189-230
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• 2020

The metabolic syndrome, by definition, is not a disease but is a clustering of individual metabolic risk factors including abdominal obesity, hyperglycemia, hypertriglyceridemia, hypertension, and low high-density lipoprotein cholesterol levels. These risk factors could dramatically increase the prevalence of type 2 diabetes and cardiovascular disease. The reported prevalence of the metabolic syndrome varies, greatly depending on the definition used, gender, age, socioeconomic status, and the ethnic background of study cohorts. Clinical and epidemiological studies have clearly demonstrated that the metabolic syndrome starts with central obesity. Because the prevalence of obesity has doubly increased worldwide over the past 30 years, the prevalence of the metabolic syndrome has markedly boosted in parallel. Therefore, obesity has been recognized as the leading cause for the metabolic syndrome since it is strongly associated with all metabolic risk factors. High prevalence of the metabolic syndrome is not unique to the USA and Europe and it is also increasing in most Asian countries. Insulin resistance has elucidated most, if not all, of the pathophysiology of the metabolic syndrome because it contributes to hyperglycemia. Furthermore, a major contributor to the development of insulin resistance is an overabundance of circulating fatty acids. Plasma fatty acids are derived mainly from the triglycerides stored in adipose tissues, which are released through the action of the cyclic AMP-dependent enzyme, hormone sensitive lipase. This review summarizes the latest concepts in the definition, pathogenesis, pathophysiology, and diagnosis of the metabolic syndrome, as well as its preventive measures and therapeutic strategies in children and adolescents.