• Transactions of the Korean Society of Mechanical Engineers A
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• v.30 no.11 s.254
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• pp.1447-1454
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• 2006

The evaluation of parallel performance of a high speed impact simulation is not an easy task because not only the development of parallel explicit code is difficult but also a large number of processors is not easily accessible. In this paper, the parallel performance of a new Lagrangian FEM impact code carried out on cluster supercomputer has been described in high speed range. In the case of metal sphere impacting to oblique plate, the overall speed-up continuously increases even up to 128 CPUs. Investigation of elapsed time of each part reveals that most of the inefficiency comes from the load imbalance of contact.

• The Transactions of the Korean Institute of Power Electronics
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• v.13 no.5
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• pp.336-343
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• 2008

This paper proposes a novel sensorless control scheme for a Permanent Magnet Synchronous Motor (PMSM) by using a parallel reduced-order Extended Kalman Filter. The proposed scheme can obtain rotor position and speed by back-EKF that is estimated by reduced-order ETD and save computation time great)y due to using a parallel structure that works by turns every sampling time. Therefore, proposed scheme has merits of conventional EKF, and problems of parameter sensitivity are partially overcome. And proposed scheme can safely estimate rotor speed and position by using new algorithms according to driving regions. Experimental results show the validity of the proposed estimation technique, and to verify the merit of the proposed scheme, a comparison of a new reduced-order EKF algorithm with a conventional EKF algorithm has been also made in terms of computation time.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.49 no.6
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• pp.322-329
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• 2000

BIST(Built-in Self Test) has been considered as the most promising DFT(design-for-test) scheme for the present and future test strategy. The most serious problem in applying BIST(Built-in Self Test) into a large circuit is the excessive increase in test time. This paper is focused on this problem. We proposed a new BIST construction scheme which uses a parallel divide-and-conquer method. The circuit division is performed with respect to some internal nodes called test points. The test points are selected by considering the nodal connectivity of the circuit rather than the testability of each node. The test patterns are generated by only one linear feedback shift register(LFSR) and they are shared by all the divided circuits. Thus, the test for each divided circuit is performed in parallel. Test responses are collected from the test point as well as the primary outputs. Even though the divide-and-conquer scheme is used and test patterns are generated in one LFSR, the proposed scheme does not lose its pseudo-exhaustive property. We proposed a selection procedure to find the test points and it was implemented with C/C++ language. Several example circuits were applied to this procedure and the results showed that test time was reduced upto 1/2151 but the increase in the hardware overhead or the delay increase was not much high. Because the proposed scheme showed a tendency that the increasing rates in hardware overhead and delay overhead were less than that in test time reduction as the size of circuit increases, it is expected to be used efficiently for large circuits as VLSI and ULSI.

• Journal of the Korea Society of Computer and Information
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• v.19 no.12
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• pp.1-10
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• 2014

This paper proposes a scheduling scheme that enhances power consumption efficiency of periodic real-time tasks using DVFS and power-shut-down mechanisms while meeting their deadlines on multicore processors. The proposed scheme is suitable for dependent multicore processors in which processing cores have an identical speed at an instant, and resolves the load unbalance of processing cores by exploiting parallel processing because the load unbalance causes inefficient power consumption in previous methods. Also the scheme activates a part of processing cores and turns off the power of unused cores. The number of activated processing cores is determined through mathematical analysis. Evaluation experiments show that the proposed scheme saves up to 77% power consumption of the previous method.

• The Transactions of the Korean Institute of Power Electronics
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• v.16 no.3
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• pp.266-273
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• 2011

This paper proposes a novel sensorless control scheme for a Permanent Magnet Synchronous Motor (PMSM) by using a parallel reduced-order Extended Kalman Filter. The proposed scheme can obtain rotor position and speed by back-EMF that is estimated by reduced-order EKF and save computation time greatly due to using a parallel structure that works by turns every sampling time. Therefore, proposed scheme has merits of conventional EKF, and problems of parameter sensitivity are partially overcome. And proposed scheme can safely estimate rotor speed and position by using new algorithms according to driving regions. Experimental results show the validity of the proposed estimation technique, and to verify the merit of the proposed scheme, a comparison of a new reduced-order EKF algorithm with a conventional EKF algorithm has been also made in terms of computation time.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.10
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• pp.27-35
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• 1997

In this paper, we propose a new scheme for the generation of partial products for VLSI fast parallel multiplier. It adopts a new encoding method which halves the number of partial products using 2x2 submultipliers and rearrangement of primitive partial products. The true 4-input CSA can be achieved with appropriate rearrangement of primitive partial products out of 2x2 submultipliers using the newly proposed theorem on binary number system. A 16bit x 16bit multiplier has been desinged using the proposed method and simulated to prove that the method has comparable speed and area compared to booth's encoding method. Much smaller and faster multiplier could be obtained with far optimization. The proposed scheme can be easily extended to multipliers with inputs of higher resolutions.

• Proceedings of the KIPE Conference
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• 1998.10a
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• pp.276-280
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• 1998

This paper proposes a harmonic a harmonic reduction technique of the parallel-connected twelve-pulse thyristor rectifiers. The proposed system is an improvement over the diode rectifier system with an active interphase reactor [2]. In this scheme, a low KVA (0.15 Po (PU) ) active current source injects a triangular current into an interphase reactor of a twelve-pulse thyristor rectifier along the phase delay angle. The current injection results in near sinusoidal input current with less than 1% THD. Detailed analysis of the proposed scheme along scheme along with design equations is illustrated. Simulation results verify the concept.

• Journal of the Institute of Convergence Signal Processing
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• v.2 no.4
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• pp.65-70
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• 2001

In this paper a new scheme combining the turbo coder with parallel interference canceller, which effectively mitigates the effects of multiple access interferences and Ralyeigh fades in the DS-CDAM mobile communication systems is proposed Using the Monte-Carlo simulation, the performance of this scheme in terms of the number of users and signal to noise ration under AWGN and Ralyeigh fading environment is analyzed. The results of simulations show that the proposed scheme outperforms conventional CDMA receiver systems over Rayleigh fading as well as AWGN.

• Proceedings of the IEEK Conference
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• 2003.11c
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• pp.113-116
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• 2003

In this paper, we propose a dynamic parallel channel allocation mechanism that dynamically controls total number of allocation channels of each subscriber to effectively service user bandwidth demands while high utilization and fairness are guaranteed in WDM based optical access networks. The logical performance gain of statistical multiplexing by dynamic channel allocation is validated with analytic method as well as simulations. We also introduce the adaptive padding scheme in order to efficiently distribute forwarded frames to aggregated multi-link channels which are formed by parallel channel allocation mechanism. The proposed scheme shows the performance enhancement by minimizing unnecessary padding size and the processing time.

• Proceedings of the KIEE Conference
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• 1996.07b
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• pp.1034-1036
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• 1996

In this paper, an adaptive fuzzy logic controller is presented for auto-tunning of the scaling factors by using learning capability of neural networks. The proposed scheme consists of the FLC which includes the PI-type FLC and PD-type FLC in parallel form and the neural network which learns scale factors of FLC. Computer simulations were performed to illustrate the effectiveness of a proposed scheme. A proposed FLC controller was applied to the second order system and velocity control of the brushless DC motors. For the design of the FLC, tracking error, change of error, and acceleration error are selected as input variables of the FLC and three seal e factors were used in the parallel-type FLC. This scheme can be used to reduce the difficulty in the selection of the scale factors.