• Proceedings of the KIEE Conference
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• 2001.07a
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• pp.233-236
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• 2001

Parallel operation scheme to several transformers is adopted because of the load increase, economic problem, or load shedding. For the transformer's parallel operation, loads proportional to each transformer's capacity must be allotted, and circulation currents must be limited as much as without causing any problem in a real operation. But, both transformers in parallel operation can be tripped when either faults at lower voltage side of a transformer or faults in a bus occurs. Therefore, parallel operation scheme to distribution transformers in Korea is not adopted in a normal state but only when loaded or load-shedded. These are due to the insufficiency of the construction in communication network and AVR scheme. Besides that, those are because bus bar protection scheme to lower voltage side of a transformer is not applied. In spite of enormous initial investment costs, advanced countries take so much account of power system reliability and stable supply that they adopt the parallel operation scheme in a normal state. One of the problems in parallel operation is the overheat of transformers due to the excessive circulation currents. This paper presents the scheme that controls voltages between both transformers using circulation currents that occurs in parallel operation.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.12 no.1
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• pp.497-522
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• 2018

Fully homomorphic encryption(FHE) scheme may be the best method to solve the privacy leakage problem in the untrusted servers because of its ciphertext calculability. However, the existing FHE schemes are still not being put into the practical applications due to their low efficiency. Therefore, it is imperative to find a more efficient FHE scheme or to optimize the existing FHE schemes so that they can be put into the practical applications. In this paper, we optimize GSW scheme by using the parallel computing, and finally we get a high-performance FHE scheme, namely PGSW scheme. Experimental results show that the time overhead of the homomorphic operations in new FHE scheme will be reduced manyfold with the increasing of processing units number. Therefore, our scheme can greatly reduce the running time of homomorphic operations and improve the performance of FHE scheme through sacrificing hardware resources. It can be seen that our FHE scheme can catalyze the development of FHE.

• ETRI Journal
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• v.44 no.2
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• pp.313-326
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• 2022

This study presents a noble scheme for distributed and parallel simulations with optimized agent placement for simulation instances. The traditional parallel simulation has some limitations in that it does not provide sufficient performance even though using multiple resources. The main reason for this discrepancy is that supporting parallelism inevitably requires additional costs in addition to the base simulation cost. We present a comprehensive study of parallel simulation architectures, execution flows, and characteristics. Then, we identify critical challenges for optimizing large simulations for parallel instances. Based on our cost-benefit analysis, we propose a novel approach to overcome the performance constraints of agent-based parallel simulations. We also propose a solution for eliminating the synchronizing cost among local instances. Our method ensures balanced performance through optimal deployment of agents to local instances and an adaptive agent placement scheme according to the simulation load. Additionally, our empirical evaluation reveals that the proposed model achieves better performance than conventional methods under several conditions.

• International Journal of Reliability and Applications
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• v.11 no.1
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• pp.17-22
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• 2010

It is desired to estimate the reliability of a system that has two subsystems connected in series where each subsystem has two components connected in parallel. A batch sequential sampling scheme is introduced. It is shown that the batch sequential sampling scheme is asymptotically optimal as the total number of units goes to infinity. Numerical comparisons indicate that the batch sequential sampling scheme performs better than the balanced sampling scheme and is nearly optimal.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.2
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• pp.383-393
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• 1996

This paper considers the evaluation of the ecquistion performance for an accesschannel preamble based on a random access procedure of direct sequence code division multiple access(DS/CDMA) reverse link. The parallel acquistion technique that employs the single-well detection scheme and the multiple-dwell(double-dwell) detection scheme is mentioned. The acquisition performance for two detection schemes is compared in therms of the acquisition probability and the acquisition time. The parallel acquisition is done by a bank of N parallel I/Q noncoherent correlators. Expressions on the detection, false alarm, and miss probabilities of the single-dwell and multiple-dwell(double-well) detection schemes are derived for multiple H$_{1}$ cells and multipath Rayleight fading channel. comparing the single-dwell detection scheme with the multiple-dwell(double-dwell) detection scheme in the case of employing the parallel acquisition technique in the reverse link,the numerical results show that the single-dwell detection scheme deomonstrates a better performance.

• Journal of Power Electronics
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• v.17 no.4
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• pp.1004-1013
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• 2017

This paper presents an interleaving scheme for parallel-connected power systems to reduce the DC-link current ripple. A paralleled generator system generates current ripple by the Pulse Width Modulation (PWM) of each generator side converter. The current ripple in the DC-link degrades the efficiency of the whole generator system and decreases the lifetime of the DC-link capacitors. To mitigate these issues, the expression of the DC-link current is derived by a double-integral Fourier analysis while considering the modulation schemes. Optimized interleaving angles for the parallel generator system are obtained based on an analysis to minimize the dominant current harmonics component. Finally, the proposed interleaving scheme reduces the RMS value of the DC-link current ripple. Simulation and experimental results verify the effectiveness of the proposed interleaving scheme.

• Proceedings of the KIPE Conference
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• 1998.07a
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• pp.90-94
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• 1998

The parallel inverter is popularly used because of its fault-tolerance capability, high-current outputs at constant voltages and system modularity. The conventional parallel inverter usually employes active and reactive power control or frequency and voltage droop control. However, these approaches have the disadvantages that the response time of parallel inverter control is slow against load and system parameter variation to calculate active, reactive power, frequency and voltage. This paper describes a novel control scheme for power equalization in parallel connected inverter. The proposed scheme has a fast power balance control response, a simplicity of implementation, and inherent peak current limiting capability since it employes a instantaneous current/voltage control with output voltage and current balance and output voltage regulation. A design procedure for the proposed parallel inverter controller is presented. Futhermore, the proposed control scheme is verified through the simulation in various cases such as the system parameter variation, the control parameter variation and the nonlinear load condition.

• Proceedings of the KIPE Conference
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• 1998.10a
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• pp.176-181
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• 1998

The parallel inverter is popularly used because of its fault-tolerance capability, high-current outputs at constant voltages and system modularity. The conventional parallel inverter usually employs active and reactive power control of frequency and voltage droop control. However, these approaches have the disadvantages that the response time of parallel inverter control is slow against load and system parameter variation to calculate active, reactive power, frequency and voltage. This paper describes a novel control scheme for power equalization in parallel-connected inverter. The proposed scheme has a fast power balance control response, a simplicity of implementation, and inherent peak current limiting capability since it employees an instantaneous current/voltage control with output voltage and current balance and output voltage regulation. A design procedure for the proposed parallel inverter controller is presented. Furthermore, the proposed control scheme is verified through the experiment in various cases such as the system parameter variation, the control parameter variation and the nonlinear load condition.

• Proceedings of the KIEE Conference
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• 2001.07e
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• pp.134-140
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• 2001

Parallel processing has the potential to be cost effectively used on computationally intense power system problems. But this technology is not still available is not only parallel computer but also parallel processing scheme. Testing these algorithms to ensure accuracy, and evaluation of their performance is also an issue. Although a significant amount of parallel algorithms of power system problem have been developed in last decade, actual testing on processor architectures lies in the beginning stages. This paper presents the parallel processing algorithm to supply the base being able to treat power flow by newton's method by the distributed memory type parallel computer. This method is to assign and to compute teared blocks of sparse matrix at each parallel processors. The testing to insure accuracy of developed method have been done on serial computer by trying to simulate a parallel environment.

• ETRI Journal
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• v.35 no.5
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• pp.767-774
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• 2013

In this paper, a novel parallel Viterbi decoding scheme is proposed to decrease the decoding latency and power consumption for the software-defined radio (SDR) system. It implements a divide-and-conquer approach by first dividing a block into a series of subblocks, then performing independent Viterbi decoding for each subsequence, and finally merging the surviving subpaths into the final path. Moreover, a network-on-chip-based SDR platform is used to evaluate the performance of the proposed parallel Viterbi decoding scheme. The experiment results show that our scheme can speed up the Viterbi decoding process without increasing the BER, and it performs better than the current state-of-the-art methods.