Journal of Power Electronics

The Korean Institute of Power Electronics (전력전자학회)
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An Interleaving Scheme for DC-link Current Ripple Reduction in Parallel-Connected Generator Systems

  • Jeong, Min-Gyo (Department of Electrical and Computer Engineering, Ajou University) ;
  • Shin, Hye Ung (Department of Electrical and Computer Engineering, Ajou University) ;
  • Baek, Ju-Won (Power Conversion Research Center, Korea Electrotechnology Research Institute) ;
  • Lee, Kyo-Beum (Department of Electrical and Computer Engineering, Ajou University)
  • Received : 2016.12.23
  • Accepted : 2017.04.12
  • Published : 2017.07.20
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Abstract

This paper presents an interleaving scheme for parallel-connected power systems to reduce the DC-link current ripple. A paralleled generator system generates current ripple by the Pulse Width Modulation (PWM) of each generator side converter. The current ripple in the DC-link degrades the efficiency of the whole generator system and decreases the lifetime of the DC-link capacitors. To mitigate these issues, the expression of the DC-link current is derived by a double-integral Fourier analysis while considering the modulation schemes. Optimized interleaving angles for the parallel generator system are obtained based on an analysis to minimize the dominant current harmonics component. Finally, the proposed interleaving scheme reduces the RMS value of the DC-link current ripple. Simulation and experimental results verify the effectiveness of the proposed interleaving scheme.

Keywords

References

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