• KSCE Journal of Civil and Environmental Engineering Research
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• v.33 no.2
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• pp.443-453
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• 2013

The hybrid test is one of the most advanced test methods to predict the structural dynamic behavior with the interaction between a physical substructure and a numerical modeling in the hybrid control system. The purpose of this study is to perform the multi-directional dynamic test of a steel frame structure with the real-time hybrid system and to evaluate the validation of the results. In this study, FEAPH, nonlinear finite element analysis program for hybrid only, was developed and the hybrid control system was optimized. The inefficient computational time was improved with a fixed number iteration method and parallel computational techniques used in FEAPH. Furthermore, the previously used data communication method and the interface between a substructure and an analysis program were simplified in the control system. As the results, the total processing time in real-time hybrid test was shortened up to 10 times of actual measured seismic period. In order to verify the accuracy and validation of the hybrid system, the linear and nonlinear dynamic tests with a steel framed structure were carried out so that the trend of displacement responses was almost in accord with the numerical results. However, the maximum displacement responses had somewhat differences due to the analysis errors in material nonlinearities and the occurrence of permanent displacements. Therefore, if the proper material model and numerical algorithms are developed, the real-time hybrid system could be used to evaluate the structural dynamic behavior and would be an effective testing method as a substitute for a shaking table test.

• Korean Journal of Agricultural and Forest Meteorology
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• v.21 no.1
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• pp.65-73
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• 2019

The MODIS (Moderate Resolution Imaging Spectroradiometer) data in Hierarchical Data Format (HDF) have been processed using the Geospatial Data Abstraction Library (GDAL). Because of a relatively large data size, it would be preferable to build and install the data analysis tool with greater computing performance, which would differ by operating system and the form of distribution, e.g., source code or binary package. The objective of this study was to examine the performance of the GDAL for processing the HDF files, which would guide construction of a computer system for remote sensing data analysis. The differences in execution time were compared between environments under which the GDAL was installed. The wall clock time was measured after extracting data for each variable in the MODIS data file using a tool built lining against GDAL under a combination of operating systems (Ubuntu and openSUSE), compilers (GNU and Intel), and distribution forms. The MOD07 product, which contains atmosphere data, were processed for eight 2-D variables and two 3-D variables. The GDAL compiled with Intel compiler under Ubuntu had the shortest computation time. For openSUSE, the GDAL compiled using GNU and intel compilers had greater performance for 2-D and 3-D variables, respectively. It was found that the wall clock time was considerably long for the GDAL complied with "--with-hdf4=no" configuration option or RPM package manager under openSUSE. These results indicated that the choice of the environments under which the GDAL is installed, e.g., operation system or compiler, would have a considerable impact on the performance of a system for processing remote sensing data. Application of parallel computing approaches would improve the performance of the data processing for the HDF files, which merits further evaluation of these computational methods.

• Journal of Broadcast Engineering
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• v.19 no.6
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• pp.866-876
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• 2014

Generating of digital hologram of video contents with computer graphics(CG) requires natural fusion of 3D information between real and virtual. In this paper, we propose the system which can fuse real-virtual 3D information naturally and fast generate the digital hologram of fused results using multiple-GPUs based computer-generated-hologram(CGH) computing part. The system calculates camera projection matrix of RGB-Depth camera, and estimates the 3D information of virtual object. The 3D information of virtual object from projection matrix and real space are transmitted to Z buffer, which can fuse the 3D information, naturally. The fused result in Z buffer is transmitted to multiple-GPUs based CGH computing part. In this part, the digital hologram of fused result can be calculated fast. In experiment, the 3D information of virtual object from proposed system has the mean relative error(MRE) about 0.5138% in relation to real 3D information. In other words, it has the about 99% high-accuracy. In addition, we verify that proposed system can fast generate the digital hologram of fused result by using multiple GPUs based CGH calculation.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.3_4
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• pp.149-159
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• 2003

The need for information security increases interests on cipher algorithms recently. Especially, a large volume of data transmission over high-band communication network requires faster encryption and decryption techniques for real-time processing. It would be a good solution for this problem that we implement the cipher algorithm in forms of hardware circuits. Though some previous researches use this approach, they focus only on repeatedly executing the core part of the algorithm to minimize the hardware chip size, while most cipher algorithms are inherently parallel. In this paper, we propose a new design for the SEED block cipher algorithm developed by KISA (Korea Information Security Agency) in 1998 as Korean standard cipher algorithm. It exploits the parallelism of the algorithm basically and implements it in a pipelined fashion. We described the design in VHDL program and performed functional simulations on the program, and then found that it worked correctly. In addition, we synthesized it and verified that it could be implemented in a single FPGA chip, implying that the new design can be Practically used for the actual hardware implementation of a high-speed and high-performance cipher system.

• The KIPS Transactions:PartA
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• v.10A no.6
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• pp.627-634
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• 2003

In this paper, we consider a graph-theoretic problem,, the so-called "graph embedding problem" that maps the vertices and edges of the given guest graph model into the corresponding vertices and paths of the host graph under the condition of maintaining better performance parameters such as dilation, congestion, and expansion. We firstly propose a new mapping function which can embed the pyramid model with height N into the 3-dimensional mesh massively parallel processor system with the height $(4^{(N+1)/3}+2)/3$ and the regular 2-dimensional mesh of one side $2^{(2N-1)/3}$, and analyze the performance of the embedding in terms of the dilation parameter that reflects the number of communication steps between two adjacent vertices under the embedding. We prove that the dilation of the embedding is $2{\cdot}4^{(N-2)/3}+4)/3$. This is superior to the previous result of $4^{N+183}+2)/3$ under the same condition.condition.

• The KIPS Transactions:PartA
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• v.14A no.2
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• pp.117-124
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• 2007

In this paper we present a translation lookaside buffer (TLB) system with low power consumption for embedded processors. The proposed TLB is constructed as multiple banks, each with an associated block buffer and a corresponding comparator. Either the block buffer or the main bank is selectively accessed on the basis of two bits in the block buffer (tag buffer). Dynamic power savings are achieved by reducing the number of entries accessed in parallel, as a result of using the tag buffer as a filtering mechanism. The performance overhead of the proposed TLB is negligible compared with other hierarchical TLB structures. For example, the two-cycle overhead of the proposed TLB is only about 1%, as compared with 5% overhead for a filter (micro) TLB and 14% overhead for a same structure without continuos accessing distinction algorithm. We show that the average hit ratios of the block buffers and the main banks of the proposed TLB are 95% and 5% respectively. Dynamic power is reduced by about 95% with respect to with a fully associative TLB, 90% with respect to a filter TLB, and 40% relative to a same structure without continuos accessing distinction algorithm.

• The KIPS Transactions:PartA
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• v.14A no.2
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• pp.99-106
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• 2007

Grid computing, a mechanism which uses heterogeneous systems that are geographically distributed, draws attention as a new paradigm for the next generation operation of parallel and distributed computing. The importance of grid computing concerning communication cost is very huge because grid computing furnishes uses with integrated virtual computing service, in which a number of computer systems are connected by a high-speed network. Therefore, to reduce the execution time, the scheduling algorithm in grid environment should take communication cost into consideration as well as computing ability of resources. However, most scheduling algorithms have not only ignored the communication cost by assuming that all tasks were dealt in one cluster, but also did not consider the overhead of communication cost when the tasks were processed in a number of clusters. In this paper, the functions of original scheduling algorithms are analyzed. More importantly, the functions of algorithms are compared and analyzed with consideration of communication cost within the co allocation environment, in which a task is performed separately in many clusters.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.3
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• pp.585-593
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• 2017

In this paper, we propose a deblocking filter hardware architecture for low-power HEVC (High-Efficiency Video Coding) in-loop for mobile systems. HEVC performs image compression on a block-by-block basis, resulting in blockage of the image due to quantization error. The deblocking filter is used to remove the blocking phenomenon in the image. Currently, UHD video service is supported in various mobile systems, but power consumption is high. The proposed low-power deblocking filter hardware structure minimizes the power consumption by blocking the clock to the internal module when the filter is not applied. It also has four parallel filter structures for high throughput at low operating frequencies and each filter is implemented in a four-stage pipeline. The proposed deblocking filter hardware structure is designed with Verilog HDL and synthesized using TSMC 65nm CMOS standard cell library, resulting in about 52.13K gates. In addition, real-time processing of 8K@84fps video is possible at 110MHz operating frequency, and operation power is 6.7mW.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.6
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• pp.1169-1181
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• 1994

The Gamma Network contains the redundant path thereby is provides the ability to tolerate the faults occured. However, in case of identical the source and destination number, only a single path exists, therefore there is no way of connecting for the fault situation. In addition, for the dynamic packet routing strategy, it shoed perform backtracking analysis to find the redundant path. In this paper we proposed a new network, Dual Network, to resolve these drawbacks. The Dual Network uses switching elements about the same network size as the Gamma Network except first and last stage, and it is more efficient than the Gamma Network, for it has reduced the switching stage by one. And since is used a destination tag routing scheme for the control algorithm, it has on advantage of becoming of simpler and faster routing control.

• Proceedings of the KSR Conference
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• 2010.06a
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• pp.110-115
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• 2010

Recently the deeply underground tunnels have been increased along the subway railroads of urban area compared to the past subway railroads. The Shin-Gum-Ho subway station (the Fifth lines, the depth : 46m) which is the third among the deep subway stations in the Korea was chosen as the model of deeply underground stations, and attempted to do simulation of fire. This station consists of three entrance, the basement first floor (B1), the basement second floor (B2), the basement eighth floor or platform (B8) and escalators and stairs from B2 to B8. The total number of grid was about 9,000,000 to make simulation of fire and smoke from the platform to entrance in this research, and the grid system was divided into 19 blocks to increase the efficiency of this simulation. The FDS (Fire Dynamics Simulation) was chosen to make the simulation of fire, and the model of turbulent flow was LES (Large Eddy Simulation). Each block is processed in a CPU using parallel processing of MPI (Message Passing Interface). The resource of CPU for this simulation is a ten of Intel 3.0 GHz Dual CPU (20 CPU).