• 전기전자학회논문지
• /
• 제24권4호
• /
• pp.942-949
• /
• 2020

본 논문에서는 column-parallel readout 회로에 적합하도록 개선된 CMOS 이미지 센서용 algorithmic ADC를 제안한다. 커패시터의 비율과 무관하고 연산 증폭기의 이득에 둔감하면서 증폭기 하나로 동작 할 수 있도록 기존 algorithmic ADC를 수정하고 적응형 바이어싱을 적용한 증폭기를 사용하여 높은 변환효율을 갖도록 하였다. 제안하는 ADC는 0.18-㎛ 매그나칩 CMOS 공정으로 설계되었으며, Spectre 시뮬레이션을 통해 기존 algorithmic ADC에 비해 변환속도당 전력소모가 37% 줄어 들었음을 확인하였다.

• 한국전자통신학회논문지
• /
• 제9권4호
• /
• pp.425-432
• /
• 2014

산악지형이 많은 한국 실정에서 국지적으로 발생하는 기상자료를 제공하기 위하여 진공관식 레이더 보다는 반도체를 이용한 소형의 X-band 기상레이더의 필요성이 요구되고 있다. 기상레이더의 이중 편파방식에 사용되는 반도체형 전력증폭기(SSPA)는 다수의 소출력 전력소자를 병렬로 결합함으로써 원하는 고출력을 얻을 수 있다. 이와 같이 고출력 전력증폭기에 적용되는 전력결합기는 경로손실, 고주파수, 고출력에 따른 안정저항의 문제, 열방출 특성을 해결하기 위하여 본 논문에서는 변형된 Gysel 전력결합기를 적용한 결과 격리도(isolation)의 우수성을 제시하였으며, 최대출력 54dBm, 25%의 효율을 갖는 기상레이더용 X-band 250W 급 반도체형 전력증폭기를 설계하였다.

• 정보처리학회논문지A
• /
• 제11A권2호
• /
• pp.195-202
• /
• 2004

본 연구에서 매우 정밀한 샘플링을 필요로 하는 고해상도 비디오 응용면을 위하여 병렬 파이프라인 아날로그 디지털 변환기(ADC)를 설계하였다. 본 ADC의 구조는 4 채널의 10-비트 파이프라인 ADC를 병력 time-interleave로 구성한 구조로서 이 구조에서 채널 당 샘플링 속도의 4배인 200MS/s의 샘플링 속도를 얻을 수 있었다. 변환기에서 핵심이 되는 구성요소는 Sample and Hold 증폭기(SHA), 비교기와 연산증폭기이며 먼저 SHA를 전단에 설치하여 시스템 타이밍 요구를 완화시키고 고속변환과 고속 입력신호의 처리론 가능하게 하였다. ADC 내부 단들의 1-비트 DAC, 비교기 및 2-이득 증폭기는 한 개의 switched 캐패시터 회로로 통합하여 고속동작은 물론 저 전력소비가 가능한 특성을 갖도록 하였다. 본 연구의 연산증폭기는 2단 차동구조에 부저항소자를 사용하여 높은 DC 이득을 갖도록 보강하였다. 본 설계에서 각 단에 D-플립플롭(D-FF)을 사용한 지연회로를 구성하여 변환시 각 비트신호를 정렬시켜 타이밍 오차를 최소화하였다. 된 변환기는 3.3V 공급전압에서 280㎽의 전력소비를 갖고 DNL과 INL은 각각 +0.7/-0.6LSB, +0.9/-0.3LSB이다.

• Journal of Power Electronics
• /
• 제19권3호
• /
• pp.637-644
• /
• 2019

Wireless power transfer (WPT) technology with various transfer mechanisms such as inductive coupling, magnetic resonance and capacitive coupling is being widely researched. Until now, power transfer efficiency (PTE) and power transfer capability (PTC) have been the primary concerns for designing and developing WPT systems. Therefore, a lot of studies have been documented to improve PTE and PTC. However, power consumption in the standby mode, also defined as the no-load mode, has been rarely studied. Recently, since the number of WPT products has been gradually increasing, it is necessary to develop techniques for reducing the standby power consumption of WPT systems. This paper investigates the standby power consumption of commercial WPT products. Moreover, a standby power reduction technique for WPT systems via magnetic resonance coupling (MRC) with a parallel resonance type resonator is proposed. To achieve a further standby power reduction, the voltage control of an AC/DC travel adapter is also adopted. The operational principles and characteristics are described and verified with simulation and experimental results. The proposed method greatly reduces the standby power consumption of a WPT system via MRC from 2.03 W to 0.19 W.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2001년도 하계종합학술대회 논문집(1)
• /
• pp.393-396
• /
• 2001

In this paper, a new type of linearizer using a parallel diode with a bias feed resistance has been studied. It has positive gain and negative phase deviations because of a nonlinearity of the diode and movement of bias point cause by a voltage drop at the bias feed resistance. This predistortion linearizer consists of the little component and miniaturizes circuit design. The characteristics of this linearizer can be easily tuned using input bias voltage. In fabricated linearizer, maximum gain and Phase deviation of the linearizer is 1dB, 21$^{\circ}$ respectively. By applying its characteristics to the power amplifier, it will be linearized power amplifier.

• Journal of Power Electronics
• /
• 제7권3호
• /
• pp.238-245
• /
• 2007

This paper considers the problem of regulating the output voltage of a current doubler rectified asymmetric half-bridge (CDRAHB) DC/DC converter via fuzzy integral control. First, we model the dynamic characteristics of the CDRAHB converter with the state-space averaging method, and after introducing an additional integral state of the output regulation error, we obtain the Takagi-Sugeno (TS) fuzzy model for the augmented system. Second, the concept of parallel distributed compensation is applied to the design of the TS fuzzy integral controller, in which the state feedback gains are obtained by solving the linear matrix inequalities (LMIs). Finally, numerical simulations of the considered design method are compared to those of the conventional method, in which a compensated error amplifier is designed for the stability of the feedback control loop.

• 전력전자학회:학술대회논문집
• /
• 전력전자학회 2007년도 하계학술대회 논문집
• /
• pp.247-249
• /
• 2007

This paper proposes a dry-type surface myoelectric sensor for the myoelectric hand prosthesis. The designed surface myoelectric sensor is composed of skin interface and processing circuits. The skin interface has one reference and two input electrodes, and the reference electrode is located in the center of two input electrodes. Considering the conduction velocity and the median frequency of the myoelectric signal, the inter-electrode distance (IED) between two input electrodes as 18mm, 20mm, and 22mm is selected. The signal processing circuit consists of a differential amplifier with a band pass filter, a band rejection filter for rejecting 60㎐ power-line noise, amplifier, and a level circuit. Using SUS440, six prototype skin interface with different reference electrode shape and IED is fabricated, and their output characteristics are evaluated by output signal obtained from the forearm of a healthy subject. The experimental results show that the skin interface with parallel bar shape and the 18mm IED has a good output characteristics. The fabricated dry-type surface myoelectric sensor is evaluated for the upper-limb amputee.

• Transactions on Electrical and Electronic Materials
• /
• 제2권4호
• /
• pp.1-6
• /
• 2001

In this paper, a 1.5 V high-gain high-frequency CMOS complementary operational amplifier is presented. The input stage of op-amp is designed for supporting the constant transconductance on the Input stage by consisting of the parallel-connected rail-to-rail complementary differential pairs. And consisting of the class-AB rail-to-rail output stage using the concept of elementary shunt stage and the grounded-gate cascode compensation technique for improving the low PSRR which was a disadvantage in the general CMOS complementary input stage, the load dependence of open loop gain and the stability of op- amp on the output load are improved, and the high-gain high-frequency operation can be achieved. The designed op-amp operates perfectly on the complementary mode with the 180° phase conversion for a 1.5 V supply voltage, and shows the DC open loop gain of 84 dB, the phase margin of 65°, and the unity gain frequency of 20 MHz. In addition, the amplifier shows the 0.1 % settling time of .179 ㎲ for the positive step and 0.154 ㎲ for the negative step on the 100 mV small-signal step, respectively, and shows the total power dissipation of 8.93 mW.

• 전자공학회논문지D
• /
• 제34D권8호
• /
• pp.1-7
• /
• 1997

In ahigh power amplifier design, power combiner/divider is used to connect low power amplifiers in parallel. The raidal structure of the powe combiner/divider has not only a good characteristics of port-to-port isolation but also an advantage of giving a redundancy to the structure itself by using RF switches. The parastics of a power resistor, that would be a problem in design process, are removed by both slot lines and cavity resonators, and the comon node in the circuit is rdesigned as a planar topology, and thus a new type of 4-way radial power combiner/divider is accomplished at 1840 ~ 1870 MH PCS frequency band. The insertion loss, reflection, and isolation characteristics of 40way radial power combiner/divider which can be adaptable to PCS system in this thesis are -0.3dB, -24dB,a dn -27dB respectively.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 1998년도 추계종합학술대회 논문집
• /
• pp.675-678
• /
• 1998

In this paper, power amplifiers for PCS phone were designed with the GEC Marconi H40 HEMT libray. The 1st stage was carefully designed in order to obtain k〉1 using a parallel resistor, and its S21 gain of 18.3dB and input reflection coefficient of -4dB were obtained. And S21 gain of 18dB and input reflection coefficient of -7dB were obtained from the 2nd stage. Finally, total S21 gain of 38dB, input reflection coefficient of -16dB, power gain of 35.2dB, output power of 28.7dBm and PAE(power added efficiency) of 29% were obtained from the designed MMIC power amplifiers. The chip size is $1.729$\times$0.94\textrm{mm}^2.$