• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.806-809
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• 2007

SRAM cell array and peripheral circuits on display panel are designed using LTPS process. To overcome low yield of SOP, high speed parallel fault detection circuitry for memory cells is designed at local I/O lines with minimal overhead for efficient memory cell redundancy replacement. Normal read/write and parallel test read/write are simulated and verified.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.1
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• pp.61-64
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• 2010

Footing Resistance of a 154 kV transmission towers in korea is commonly required to be less than 15 ohm to avoid lightning back-flashover accident. The periodic measurement of Footing Resistance is important to verify that the grounding performance of the towers has been maintained good. Towers are electrically connected in parallel with overhead grounding wire, therefore footing resistance of each tower will be measured after disconnecting the overhead ground wires from the towers. however, In this paper, three direct measurement methods of footing resistance are presented. There are very useful methods without disconnecting overhead ground wires from the tower under measurement. They are compared in KEPCO 154 kV transmission towers. The experimental results describe performances of them.

• 제어로봇시스템학회:학술대회논문집
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• 1991.10b
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• pp.1817-1822
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• 1991

A method of reducing overhead caused by the processor synchronization process and common memory accesses in finely grained tasks is described. We propose a scheduler which considers the preparation time during searching to minimize the redundant accesses to shared memory. Since the suggested hardware (synchronizer) determines the access order of processors and bus arbitration simultaneously by including the synchronization process into the bus arbitration process, the synchronization time vanishes. Therefore this synchronizer has no overhead caused by the processor synchronization[l]. The proposed scheduler algorithm is processed in parallel. The processes share the upper bound derived by each searching and the lower bound function is built considering the preparation time in order to eliminate as many searches as possible. An application of the proposed method to a multi-DSP system to calculate inverse dynamics for robot arms, showed that the sampling time can be twice shorter than that of the conventional one.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2004.11a
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• pp.297-299
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• 2004

In multi-ground distribution system, overhead ground wire and neutral wire are parallel connected to offer the electrical power energy and protect damage of lightning strokes. Therefore a case where the two wires become single wire, the power company can get the benefit such as installation cost saving and line fault protection by simplify of distribution line. In this paper we describe the result of impulse test in both system ; one is the present power system the other is unified power system parallel connected overhead ground wire and neutral wire. As a result of this impulse test, the present power system get lower impulse voltage than the unified power system.

• KIPS Transactions on Computer and Communication Systems
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• v.5 no.12
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• pp.439-446
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• 2016

In this paper, an efficient prediction accuracy enhancement strategy is proposed for improving the performance of the prediction-based parallel event-driven gate-level timing simulation. The proposed new strategy adopts the static double prediction and the dynamic prediction for input and output values of local simulations. The double prediction utilizes another static prediction data for the secondary prediction once the first prediction fails, and the dynamic prediction tries to use the on-going simulation result accumulated dynamically during the actual parallel simulation execution as prediction data. Therefore, the communication overhead and synchronization overhead, which are the main bottleneck of parallel simulation, are maximally reduced. Throughout the proposed two prediction enhancement techniques, we have observed about 5x simulation performance improvement over the commercial parallel multi-core simulation for six test designs.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.59 no.2
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• pp.191-196
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• 2010

The electricity distribution system in Korea is adopting a multi-grounding system. Protection of this distribution system against lightning is performed by installing overhead ground wires over the high voltage wires, and connecting the overhead ground wires to the ground every 200 m. The ground resistance in this system is limited not to exceed $50\Omega$ and overhead ground wire and neutral wire are multiple parallel lines. Although overhead ground wire and neutral wire are installed in different locations on the same pole, this circuit configuration has duplicated functions of providing a return path for unbalanced currents and protecting the distribution system against induced lightning. Therefore, the purpose of this study is to analyze the induced lightning shielding effect according to the neutral wire installation structure of a 22.9kV distribution line in order to present a new 22.9kV distribution line structure model and characteristics. This study calculated induced lightning voltage by performing numerical analysis when an overhead ground wire is present in the multi-grounding type 22.9kV distribution line structure, and calculated the induced lightning shielding effect based on this calculated induced lightning voltage. In addition, this study proposed and analyzed an improved distribution line model allowing the use of both overhead wire and neutral wire to be installed in the current distribution lines. The result of MATLAB simulation using the conditions applied by Yokoyama showed almost no difference between the induced lightning voltage developed in the current line and that developed in the proposed line. This signifies that shielding the induced lightning voltage through overhead wire makes no difference between current and proposed distribution line structures. That is, this study found that the ground resistance of the overhead wire had an effect on the induced lightning voltage, and that the induced lightning shielding effect of overhead wire is small.

• The Journal of the Acoustical Society of Korea
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• v.39 no.6
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• pp.505-514
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• 2020

Since a large amount of training data is typically needed to train Deep Neural Networks (DNNs), a parallel training approach is required to train the DNNs. The Stochastic Gradient Descent (SGD) algorithm is one of the most widely used methods to train the DNNs. However, since the SGD is an inherently sequential process, it requires some sort of approximation schemes to parallelize the SGD algorithm. In this paper, we review various efforts on parallelizing the SGD algorithm, and analyze the computational overhead, communication overhead, and the effects of the approximations.

• The Transactions of the Korea Information Processing Society
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• v.3 no.4
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• pp.766-780
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• 1996

This paper presents a mapping scheme for parallel processing using an accurate characterization of the communication overhead. A set of objective functions is formulated to evaluate the optimality of mapping a problem graph into a system graph. One of them is especially suitable for real-time applications of parallel processing. These objective functions are different from the conventional objective functions in that the edges in the problem graph are weighted and the actual distance rather than the nominal distance for the edges in the system graph is employed. This facilitates a more accurate qualification of the communication overhead. An efficient mapping scheme has been developed for the objective functions, where two levels of assignment optimization procedures are employed: initial assignment and pairwise exchange. The mapping scheme has been tested using the hypercube as a system graph.

• Journal of Information Processing Systems
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• v.8 no.2
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• pp.331-346
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• 2012

Task-based programming is becoming the state-of-the-art method of choice for extracting the desired performance from multi-core chips. It expresses a program in terms of lightweight logical tasks rather than heavyweight threads. Intel Threading Building Blocks (TBB) is a task-based parallel programming paradigm for multi-core processors. The performance gain of this paradigm depends to a great extent on the efficiency of its parallel constructs. The parallel overheads incurred by parallel constructs determine the ability for creating large-scale parallel programs, especially in the case of fine-grain parallelism. This paper presents a study of TBB parallelization overheads. For this purpose, a TBB micro-benchmarks suite called TBBench has been developed. We use TBBench to evaluate the parallelization overheads of TBB on different multi-core machines and different compilers. We report in detail in this paper on the relative overheads and analyze the running results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.10
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• pp.2043-2052
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• 1994

This paper proposes a new parallel ASIC architecture for real-time image processing to reduce inter-processing element (inter-PE) communication overhead, called a Sliding Memory Plane (SliM) Image Processor. The Slim Image Processor consists of $3\times3$ processing elements (PEs) connected by a mesh topology. With easy scalability due to the topology. a set of SliM Image Processors can form a mesh-connected SIMD parallel architecture. called the SliM Array Processor. The idea of sliding means that all pixels are slided into all neighboring PEs without interrupting PEs and without a coprocessor or a DMA controller. Since the inter-PE communication and computation occur simultaneously. the inter-PE communication overhead, significant disadvantage of existing machines greatly diminishes. Two I/O planes provide a buffering capability and reduce the date I/O overhead. In addition, using the by-passing path provides eight-way connectivity even with four links. with these salient features. SliM shows a significant performance improvement. This paper presents architectures of a PE and the SliM Image Processor, and describes the design of an instruction set.