• 전기전자학회논문지
• /
• 제20권1호
• /
• pp.89-93
• /
• 2016

본 논문에서는 다양한 영상 전처리 알고리즘들을 적용할 수 있고, 영상 인식과 같이 ISP 응용 프로그램을 병렬로 처리 가능한 SIMT(Single Instruction Multiple Threads) 기반 Image Signal Processor를 제안하였다. 기존의 ISP는 입력 영상의 품질 개선을 위하여 영상 개선 알고리즘이 하드웨어로 설계되어 처리 속도는 빠르지만 다양한 영상 처리 알고리즘에 따라 성능 최적화에 어려움이 있었다. 제안한 ISP는 명령어를 기반으로 한 프로세서로서 다양한 영상 처리 알고리즘을 수행하고 SIMT 구조를 적용하여 알고리즘을 병렬로 수행해 성능을 개선하였다. 제안하는 ISP를 검증하기 위해 Xilinx Virtex-7을 탑재한 VC707 Board를 사용하였으며 cell multicore processor와 비교했을 경우 수행시간이 약 71%, ARM Cortex-A9과 ARM Cortex-A15와 비교하였을 경우 각각 63%, 33% 성능을 개선하였다.

• 한국군사과학기술학회지
• /
• 제25권4호
• /
• pp.372-380
• /
• 2022

This study proposes a distributed parallel processing system, called the Fast Analysis System for remote sensing daTa(FAST), for large-scale satellite image processing and analysis. FAST is a system that designs jobs in vertices and sequences, and distributes and processes them simultaneously. FAST manages data based on the Hadoop Distributed File System, controls entire jobs based on Apache Spark, and performs tasks in parallel in multiple slave nodes based on a docker container design. FAST enables the high-performance processing of progressively accumulated large-volume satellite images. Because the unit task is performed based on Docker, it is possible to reuse existing source codes for designing and implementing unit tasks. Additionally, the system is robust against software/hardware faults. To prove the capability of the proposed system, we performed an experiment to generate the original satellite images as ortho-images, which is a pre-processing step for all image analyses. In the experiment, when FAST was configured with eight slave nodes, it was found that the processing of a satellite image took less than 30 sec. Through these results, we proved the suitability and practical applicability of the FAST design.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2003년도 하계종합학술대회 논문집 Ⅲ
• /
• pp.1685-1688
• /
• 2003

The modem multimedia applications which are video Processor, video conference or video phone and so forth require real time processing. Because of a large amount of image data, those require high compression performance. In this paper, the proposed image processing encoder was designed by using wavelet transform encoding. The proposed filter block can process image data on tile high speed because of composing individual function blocks by parallel and compute both highpass and lowpass coefficient in the same clock cycle. When image data is decomposed into multiresolution, the proposed scheme needs external memory and controller to save intermediate results and it can operate within 33㎒.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• 제8권3호
• /
• pp.1058-1070
• /
• 2014

There are two major ways to implement depth estimation, multiple image depth estimation and single image depth estimation, respectively. The former has a high hardware cost because it uses multiple cameras but it has a simple software algorithm. Conversely, the latter has a low hardware cost but the software algorithm is complex. One of the recent trends in this field is to make a system compact, or even portable, and to simplify the optical elements to be attached to the conventional camera. In this paper, we present an implementation of depth estimation with a single image using a graphics processing unit (GPU) in a desktop PC, and achieve real-time application via our evolutional algorithm and parallel processing technique, employing a compute shader. The methods greatly accelerate the compute-intensive implementation of depth estimation with a single view image from 0.003 frames per second (fps) (implemented in MATLAB) to 53 fps, which is almost twice the real-time standard of 30 fps. In the previous literature, to the best of our knowledge, no paper discusses the optimization of depth estimation using a single image, and the frame rate of our final result is better than that of previous studies using multiple images, whose frame rate is about 20fps.

• 반도체디스플레이기술학회지
• /
• 제22권4호
• /
• pp.59-65
• /
• 2023

Edge detection in image processing and computer vision is one of the most fundamental operations. Canny edge detection algorithm has excellent performance and is currently widely used. However, it is difficult to process the algorithm in real-time because the algorithm is complex. In this study, the equations required in the algorithm were simplified to facilitate hardware implementation, and the calculation speed was increased by using a parallel structure. In particular, the size and management of local buffers were selected in consideration of parallel processing and filter size so that data could be processed without bottlenecks. It was designed in verilog and implemented in FPGA to verify operation and performance.

• 한국인터넷방송통신학회논문지
• /
• 제16권5호
• /
• pp.1-6
• /
• 2016

영상 회전은 영상 처리나 영상 패턴 인식에서 중요한 전처리 방법 중 하나이다. 영상 회전은 회전 행렬의 곱으로 이루어 진다. 그러나 기존의 방법은 대량의 실수 연산과 삼각 함수 계산을 필요로 하므로 수행 시간이 오래 걸린다. 본 논문에서는 이 같은 두가지 주요 지체 연산과정을 제거한 새로운 고속 영상 회전 알고리즘을 제안한다. 제안된 알고리즘은 단지 2개의 전단 연산을 행하므로 매우 빠르다. 또한 최신 병렬 처리 기술인 CUDA를 적용한다. CUDA는 최근 널리 보급된 GPU를 이용한 대용량 병렬처리 계산 아키텍쳐이다. GPGPU는 그래픽 전용프로세서이므로 화소 단위의 병렬처리에 탁월한 성능을 보인다. 제안된 알고리즘은 기존의 회전 알고리즘과 다양한 크기의 영상에 대해 비교 실험한다. 실험 결과는 제안된 알고리즘이 기존의 방법보다 8배 이상의 매우 우수한 성능을 보인다.

• 융합신호처리학회논문지
• /
• 제16권3호
• /
• pp.83-89
• /
• 2015

Connected component labeling (CCL) is a mandatory step in image segmentation where objects are extracted and uniquely labeled. CCL is a computationally expensive operation and thus is often done in parallel processing framework to reduce execution time. Various parallel CCL methods have been proposed in the literature. Among them are NSZ label equivalence (NSZ-LE) method, modified 8 directional label selection (M8DLS) method, HYBRID1 method, and HYBRID2 method. Soh et al. showed that HYBRID2 outperforms the others and is the best so far. In this paper we propose a new hybrid parallel CCL algorithm termed as HYBRID3 that combines selective four directional label search (S4DLS) with label backtracking (LB). We show that the average percentage speedup of the proposed over M8DLS is around 60% more than that of HYBRID2 over M8DLS for various kinds of images.

• International Journal of Fuzzy Logic and Intelligent Systems
• /
• 제4권1호
• /
• pp.50-55
• /
• 2004

We propose an intgrated Gill environment system having only integer fuzzy operations in the consequent part and the defuzzification stage. In this paper, we also propose an integrated Gill environment system with 4 parallel fuzzy processing units to be operated in parallel on the classification of the sensed image data. In this, we solve the problems of taking longer times as the fuzzy real computations of [0, 1] by using the integer pixel conversion algorithm to convert lines of each fuzzy linguistic term to the closest integer pixels. This procedure is performed automatically in the GUI application program. As a Gill environment, PCI transmission, image data pre-processing, integer pixel mapping and fuzzy membership tuning are considered. This system can be operated in parallel manner for MIMO or MISO systems.

• 한국시뮬레이션학회논문지
• /
• 제10권3호
• /
• pp.59-70
• /
• 2001

Typical low-level image processing tasks require thousands of operations per pixel for each input image. Traditional general-purpose computers are not capable of performing such tasks in real time. Yet important features of traditional computers are not exploited by low-level image processing tasks. Since storage requirements are limited to a small number of low-precision integer values per pixel, large hierarchical memory systems are not necessary. The mismatch between the demands of low-level image processing tasks and the characteristics of conventional computers motivates investigation of alternative architectures. The structure of the tasks suggests employing an array of processing elements, one per pixel, sharing instructions issued by a single controller. In this paper we implemented various image processing filtering using the format converter. Also, we realized from conventional gray image process to color image process. This design method is based on realized the large processor-per-pixel array by integrated circuit technology This format converter design has control path implementation efficiently, and can be utilize the high technology without complicated controller hardware.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2000년도 하계종합학술대회 논문집(3)
• /
• pp.173-176
• /
• 2000

In this study, a new multimedia data converter is proposed. Also the PC interfacing met hod using the parallel port of is suggested. The image compression/decompression is based on the JPEG algorithm, which is widely used for an effective compression in the image processing industry. The suggested interfacing method is based on the IEEE1284 and IEEE1284.3 protocol, which is a standard in the PC's parallel port interface.