• 제목/요약/키워드: Parallel Image Processing

검색결과 341건 처리시간 0.022초

영상 처리 기법을 위한 병렬화 네트워크 시스템의 구성 (Realization of a Parallel Network System for Image Processing Techniques)

  • 서원찬;조강현;김우열
    • 제어로봇시스템학회논문지
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    • 제6권6호
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    • pp.492-499
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    • 2000
  • In this paper, realization techniques of the parallel processing and the parallel network system for image processing are described. The parallel image processing system is constructed by the characterization of image processing and processor. Several problems are solved to achieve effective parallel processing and processor networking with the particular properties of image processing, which are reduction of communication quantity, equalization of load and delay depreciation on communication. A parallel image input device is developed for the flexible networking of parallel image processing. An abnormal region detection algorithm which is the basic function in machine vision is applied to evaluate the constructed parallel image processing system. The performance and effectiveness of the system are confirmed by experiments.

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영상처리를 위한 Pipelined 병렬처리 시스템 (Pipelined Parallel Processing System for Image Processing)

  • 이형;김종배;최성혁;박종원
    • 전기전자학회논문지
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    • 제4권2호
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    • pp.212-224
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    • 2000
  • 본 논문에서는 영상 응용프로그램의 처리 속도를 향상하기 위한 병렬처리 시스템을 제안한다. 병렬처리 시스템은 Pipelined SIMD 구조를 갖고 있으며, 다수개의 처리기와 다중접근 기억장치로 구성된다. 다중접근 기억장치는 메모리 모듈들과 메모리 제어부로 구성되며, 메모리 제어부는 메모리 모듈 선택 모듈, 데이터 라우팅 모듈, 그리고 주소 계산 및 라우팅 모듈로 구성되어 있으며, 블록, 행, 그리고 열 내의 데이터를 동시에 접근할 수 있는 기능을 제공한다. 제안한 병렬처리 시스템을 검증하기 위해서 형태학적 필터를 적용하여 기능 검증 및 처리속도를 확인하였다.

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Design of Parallel Processor for Image Processing

  • 노석환;박종원
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2006년도 하계종합학술대회
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    • pp.743-744
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    • 2006
  • This paper presents implementation of parallel processing system for image processing. The parallel processing system proposed consisted of 16 processing elements, and multi-access memory system, and interface modules. The multi-access memory system we introduced is made up of a memory module selection, a data routing module, and an address calculation and routing module.

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병렬처리 기반 정지영상 인식자 생성 (Parallel Processing based Image Identifier Generation)

  • 고미은;박제호;박용범;서원택
    • 반도체디스플레이기술학회지
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    • 제16권1호
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    • pp.6-10
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    • 2017
  • Recent enhancement in the still image acquisition devices has been widely perpetrated into the daily life of the common people. Due to this trend, the voluminous still images, that are produced and shared in the personal or the massive storage, need to controlled with effective and efficient management. The human-devised or system-generated still image identifiers used for the identification of the images are at risk in the situation of unexpected changing or eliminating of the identifiers. In this paper, we propose a parallel processing based method for still image identifier generation by utilizing the still image internal features.

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Novel Parallel Approach for SIFT Algorithm Implementation

  • Le, Tran Su;Lee, Jong-Soo
    • Journal of information and communication convergence engineering
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    • 제11권4호
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    • pp.298-306
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    • 2013
  • The scale invariant feature transform (SIFT) is an effective algorithm used in object recognition, panorama stitching, and image matching. However, due to its complexity, real-time processing is difficult to achieve with current software approaches. The increasing availability of parallel computers makes parallelizing these tasks an attractive approach. This paper proposes a novel parallel approach for SIFT algorithm implementation using a block filtering technique in a Gaussian convolution process on the SIMD Pixel Processor. This implementation fully exposes the available parallelism of the SIFT algorithm process and exploits the processing and input/output capabilities of the processor, which results in a system that can perform real-time image and video compression. We apply this implementation to images and measure the effectiveness of such an approach. Experimental simulation results indicate that the proposed method is capable of real-time applications, and the result of our parallel approach is outstanding in terms of the processing performance.

Performance Study of Satellite Image Processing on Graphics Processors Unit Using CUDA

  • Jeong, In-Kyu;Hong, Min-Gee;Hahn, Kwang-Soo;Choi, Joonsoo;Kim, Choen
    • 대한원격탐사학회지
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    • 제28권6호
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    • pp.683-691
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    • 2012
  • High resolution satellite images are now widely used for a variety of mapping applications including photogrammetry, GIS data acquisition and visualization. As the spectral and spatial data size of satellite images increases, a greater processing power is needed to process the images. The solution of these problems is parallel systems. Parallel processing techniques have been developed for improving the performance of image processing along with the development of the computational power. However, conventional CPU-based parallel computing is often not good enough for the demand for computational speed to process the images. The GPU is a good candidate to achieve this goal. Recently GPUs are used in the field of highly complex processing including many loop operations such as mathematical transforms, ray tracing. In this study we proposed a technique for parallel processing of high resolution satellite images using GPU. We implemented a spectral radiometric processing algorithm on Landsat-7 ETM+ imagery using CUDA, a parallel computing architecture developed by NVIDIA for GPU. Also performance of the algorithm on GPU and CPU is compared.

세포 외곽선 추출 알고리즘의 병렬화 (Parallelization of Cell Contour Line Extraction Algorithm)

  • 이호석;유숙현;권희용
    • 한국멀티미디어학회논문지
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    • 제18권10호
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    • pp.1180-1188
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    • 2015
  • In this paper, a parallel cell contour line extraction algorithm using CUDA, which has no inner contour lines, is proposed. The contour of a cell is very important in a cell image analysis. It could be obtained by a conventional serial contour tracing algorithm or parallel morphology operation. However, the cell image has various damages in acquisition or dyeing process. They could be turn into several inner contours, which make a cell image analysis difficult. The proposed algorithm introduces a min-max coordinates table into each CUDA thread block, and removes the inner contour in parallel. It is 4.1 to 7.6 times faster than a conventional serial contour tracing algorithm.

Feasibility Study of a Distributed and Parallel Environment for Implementing the Standard Version of AAM Model

  • Naoui, Moulkheir;Mahmoudi, Said;Belalem, Ghalem
    • Journal of Information Processing Systems
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    • 제12권1호
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    • pp.149-168
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    • 2016
  • The Active Appearance Model (AAM) is a class of deformable models, which, in the segmentation process, integrates the priori knowledge on the shape and the texture and deformation of the structures studied. This model in its sequential form is computationally intensive and operates on large data sets. This paper presents another framework to implement the standard version of the AAM model. We suggest a distributed and parallel approach justified by the characteristics of the model and their potentialities. We introduce a schema for the representation of the overall model and we study of operations that can be parallelized. This approach is intended to exploit the benefits build in the area of advanced image processing.

Analysis of Implementing Mobile Heterogeneous Computing for Image Sequence Processing

  • BAEK, Aram;LEE, Kangwoon;KIM, Jae-Gon;CHOI, Haechul
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • 제11권10호
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    • pp.4948-4967
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    • 2017
  • On mobile devices, image sequences are widely used for multimedia applications such as computer vision, video enhancement, and augmented reality. However, the real-time processing of mobile devices is still a challenge because of constraints and demands for higher resolution images. Recently, heterogeneous computing methods that utilize both a central processing unit (CPU) and a graphics processing unit (GPU) have been researched to accelerate the image sequence processing. This paper deals with various optimizing techniques such as parallel processing by the CPU and GPU, distributed processing on the CPU, frame buffer object, and double buffering for parallel and/or distributed tasks. Using the optimizing techniques both individually and combined, several heterogeneous computing structures were implemented and their effectiveness were analyzed. The experimental results show that the heterogeneous computing facilitates executions up to 3.5 times faster than CPU-only processing.

영상처리용 16개의 처리기를 위한 다중접근기억장치 및 병렬처리기의 칩 설계 (Design to Chip with Multi-Access Memory System and Parallel Processor for 16 Processing Elements of Image Processing Purpose)

  • 임재호;박성미;박종원
    • 한국멀티미디어학회논문지
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    • 제14권11호
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    • pp.1401-1408
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    • 2011
  • 본 논문에서는 영상처리용 16개의 처리기를 위한 다중접근기억장치(Multi-Access Memory System) 및 병렬처리기의 칩을 설계하였다. 다중접근기억장치는 병렬접근 메모리 시스템의 한 종류로서 영상의 픽셀 데이터값에 8가지 타입으로 동시 접근이 가능하다. 또한 일정한 간격을 두고 픽셀 데이터값에 접근하는 것이 가능하다. 다중접근기억장치가 내장된 병렬처리기는 실제로 2003년에 구현되어진 적이 있다. 하지만 고해상도 영상을 실시간으로 처리하기에는 그 성능이 미치지 못하였다. 이에 본 논문에서는 이전의 시스템의 메모리 모듈(Memory Module)과 처리기(Processing Element)를 추가 확장하여 보다 개선된 병렬처리 시스템을 설계하였다. 이 시스템은 이전의 시스템보다는 3배, 시리얼 시스템보다는 6배 빠른 속도로 모폴로지컬 클로징(Morphological closing) 알고리즘의 수행이 가능하다.