• Proceedings of the IEEK Conference
• /
• 2000.07a
• /
• pp.478-481
• /
• 2000

In this paper, we propose a joint coding system for still images using source coding and powerful error correcting code schemes. Our system comprises an LVQ (lattice vector quantization) source coding for wavelet transformed images and turbo coding for channel coding. The parameters of the image encoder and channel encoder have been optimized for an n-D (dimension) cubic lattice (D$_{n}$, Z$_{n}$), parallel concatenation fur two simple RSC (recursive systematic convolutional code) and an interleaver. For decoding the received image in the case of the AWGN (additive white gaussian noise) channel, we used an iterative joint source-channel decoding algorithm for a SISO (soft-input soft-output) MAP (maximum a posteriori) module. The performance of transmission system has been evaluated in the PSNR, BER and iteration times. A very small degradation of the PSNR and an improvement in BER were compared to a system without joint source-channel decoding at the input of the receiver.ver.

• IEIE Transactions on Smart Processing and Computing
• /
• v.3 no.3
• /
• pp.142-152
• /
• 2014

Vehicular Ad-hoc Networks (VANETs) are comprised of wireless mobile nodes characterized by a randomly changing topology, high mobility, availability of geographic position, and fewer power constraints. Orthogonal Frequency Division Multiplexing (OFDM) is a promising candidate for the physical layer of VANET because of the inherent characteristics of the spectral efficiency and robustness to channel impairments. The susceptibility of OFDM to Inter-Carrier Interference (ICI) is a challenging issue. The high mobility of nodes in VANET causes higher Doppler shifts, which results in ICI in the OFDM system. In this paper, a frequency domain com-btype channel estimation was used to cancel out ICI. The channel frequency response at the pilot tones was estimated using a Least Square (LS) estimator. An efficient interpolation technique is required to estimate the channel at the data tones with low interpolation error. This paper proposes a robust interpolation technique to estimate the channel frequency response at the data subcarriers. The channel induced noise tended to degrade the Bit Error Rate (BER) performance of the system. Parallel concatenated Convolutional codes were used for error correction. At the decoding end, different decoding algorithms were considered for the component decoders of the iterative Turbo decoder. A performance and complexity comparison among the various decoding algorithms was also carried out.

• 한국정보통신설비학회:학술대회논문집
• /
• 2005.08a
• /
• pp.417-421
• /
• 2005

In the recent digital communication systems, the performance of Turbo Code using the error correction coding depends on the interleaver influencing the free distance determination and the recursive decoding algorithms that is executed in the turbo decoder. However, performance depends on the interleaver depth that needs many delays over the reception process. Moreover, turbo code has been known as the robust coding methods with the confidence over the fading channel. International Telecommunication Union(ITU) has recently adopted it as the standardization of the channel coding over the third generation mobile communications(IMT-2000). Therefore, in this paper, we proposed the interleaver that has the better performance than existing block interleaver, and modified turbo decoder that has the parallel concatenated structure using MAP algorithm. In the real-time voice and video service over third generation mobile communications, the performance of the proposed two methods was analyzed and compared with the existing methods by computer simulation in terms of reduced decoding delay using the variable decoding method over AWGN and fading channels for CDMA environments.

• Journal of Broadcast Engineering
• /
• v.18 no.6
• /
• pp.816-822
• /
• 2013

The latest video coding standard HEVC was developed by the joint work of JCT-VC(Joint Collaborative Team on Video Coding) from ITU-T VCEG and ISO/IEC MPEG. The HEVC standard reduces the BD-Bitrate of about 50% compared with the H.264/AVC standard. However, using the various methods for obtaining the coding gains has increased complexity problems. The proposed method reduces the complexity of HEVC by using both CPU parallel processing and GPU-accelerated processing. The experiment result for UHD($3840{\times}2144$) video sequences achieves 15fps encoding/decoding performance by applying the proposed method. Sooner or later, we expect that the H/W speedup of data transfer rates between CPU and GPU will result in reducing the encoding/decoding times much more.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.11 no.3
• /
• pp.1684-1699
• /
• 2017

The deblocking filter (DF) reduces blocking artifacts in encoded video sequences, and thereby significantly improves the subjective and objective quality of videos. Statistics show that the DF accounts for 5-18% of the total decoding time in high-efficiency video coding. Therefore, speeding up the DF will improve codec performance, especially for the decoder. In view of the rapid development of multicore technology, we propose a parallel DF scheme based on a modified order of accessing the coding tree units (CTUs) by analyzing the data dependencies between adjacent CTUs. This enables the DF to run in parallel, providing accelerated performance and more flexibility in the degree of parallelism, as well as finer parallel granularity. We additionally solve the problems of variable privatization and thread synchronization in the parallelization of the DF. Finally, the DF module is parallelized based on the HM16.1 reference software using OpenMP technology. The acceleration performance is experimentally tested under various numbers of cores, and the results show that the proposed scheme is very effective at speeding up the DF.

• Proceedings of the IEEK Conference
• /
• 2001.06d
• /
• pp.41-44
• /
• 2001

Variable length coding (VLC) has been used in many well known standard video coding algorithms such as MPEG and H.26x. However, VLC can not be processed parallelly because of its sequentiality. This sequentiality is a big barrier for implementing a real-time software video codec since parallel schemes can not be applied. In this paper, we propose a new fast VLD (Variable Length Decoding) method based on the probabilistic distribution of symbols in VLC tables used in MPEG as well as H.263 standard codecs. Even though MPEG suggests the table partitioning method, they do not show theoretically why the number of partitioned tables is two or three. We suggest the method for deciding the number of partitioned tables. Applying our scheme to several well-known MPEG-2 test sequences, we can reduce the computational time up to about 10% without any sacrificing video quality

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.47 no.11
• /
• pp.36-42
• /
• 2010

This paper presents a hybrid approach to the construction of quasi-cyclic (QC) low-density parity-check (LDPC) codes based on parallel bundles in Euclidean geometries and circulant permutation matrices. Codes constructed by this method are shown to be regular with large girth and low density. Simulation results show that these codes perform very well with iterative decoding and achieve reasonably large coding gains over uncoded system.

• Journal of the Korean Institute of Telematics and Electronics B
• /
• v.30B no.11
• /
• pp.17-26
• /
• 1993

In this paper, a VlSI architecture for Reed-Solomon (RS) decoder based on the Berlekamp algorithm is proposed. The proposed decoder provided both erasure and error correcting capability. In order to reduc the chip area, we reformulate the Berlekamp algorithm. The proposed algorithm possesses a recursive structure so that the number of cells for computing the errata locator polynomial can be reduced. Moreover, in our approach, only one finite field multiplication per clock cycle is required for implementation, provided an improvement in the decoding speed, and the overall architecture features parallel and pipelined structure, making a real time decoding possible. From the performance evaluation, it is concluded that the proposed VLSI architecture is more efficient in terms of VLSI implementation than the rcursive architecture based on the Euclid algorithm.

• The Transactions of the Korea Information Processing Society
• /
• v.7 no.1
• /
• pp.306-312
• /
• 2000

In this paper, the efficient architecture of small Reed-solomon architecture is suggested. Here, 3-stage pipeline is adopted. In decoding, error-location polynomials are obtained by BMA using fast iteration method, and syndrome polynomials, where calculation complexity is required, are obtained by parallel calculation using ROM table, and the roots of error location polynomial are calculated by ROM table using Chein search algorithm. In the suggested decoder, it is confirmed that 3 symbol random errors can be corrected and 124Mbps decoding rate is obtained using 25 Mhz system clock.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.31A no.8
• /
• pp.111-121
• /
• 1994

This paper proposes a memory testable code called MTA(Memory TestAble) code which is based on error correcting code technique for testing functional faults in semiconductor memories. The characteristics of this code are analyzed and compared with those of conventional codes. The developed decoding technique for this code can reduce the decoder circuits up to 70% and obtain two-times faster decoding speed than other codes such as hamming code or Hsiao code. The MTA code is eccectively applicable to parallel testing of semiconductor memories because it has the same information length and parity length. It can detect from single error functional faults to triple error in semiconductor memories.