• The Journal of the Acoustical Society of Korea
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• v.38 no.1
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• pp.9-22
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• 2019

In this paper, we propose a method that can be applied to the efficient implementation of multi-channel active noise controller. Since the normalized MFxLMS (Modified Filtered-x Least Mean Square) algorithm for the multi-channel active noise control requires a large amount of computation, the difficulty has lied in implementing the algorithm using a low-cost MCU (Microcontoller Unit). We implement the multi-channel active noise controller efficiently by optimizing the software based on the features of the MCU. By maximizing the usage of single-cycle MAC (Multiply- Accumulate) operations and minimizing move operations of the delay memory, we can achieve more than 3 times the performance in the aspect of computational optimization, and by parellel processing using the auxillary processor included in the MCU, we can also obtain more than 4 times the performance. In addition, the usage of additional parts can be minimized by maximizing the usage of the peripherals embedded in the MCU.

• Proceedings of the KIPE Conference
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• 2011.07a
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• pp.179-180
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• 2011

This paper focuses on the Current-Voltage concurrent control method devoted to the multiple LED (light-emitting diode) string driver. Isolated DC to DC converter with cascaded chopping switch is proposed for smart lighting system such as light with sensor or back light unit of display, which need to control the current of parallel connected multiple LED stings and regulate DC voltage for micro controller for brightness control. The proposed circuit regulates the current of parallel connected multiple LED strings and additional DC voltage output simultaneously. To verify the performance, experimental results are presented based on the prototype board. 5V, 1A voltage mode electric load and two LED strings with different forward voltages are used for output loads. 23W output power is achieved and measured efficiency is in the range of 85%-87%

• Proceedings of the KIEE Conference
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• 2006.07a
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• pp.220-221
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• 2006

This paper presents a single-phase parallel active power filter with an analog control circuit to eliminate for harmonic source currents generated by nonlinear loads. The proposed system removes the harmonic source currents by injecting a compensation current that is 180' out of phase with the load harmonic current. The detection of the load harmonics is realized by a simple new structure, referred to the Notch Filter with GIC (Generalized Impedance Converter), which has higher Q than existing harmonic detecters and a simpler structure. The compensation current is obtained using the proposed harmonic detection circuit, DC-Link voltage, and output current of the full-bridge inverter controlled current mode PWM controller. The operation of the proposed system is verified experimentally.

• Journal of the Korea Institute of Military Science and Technology
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• v.9 no.1 s.24
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• pp.50-59
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• 2006

Lately, there exist growing demands for the use of CTAs(Cased Telescoped Ammunitions) to increase the firepower of mid-calibre automatic guns despite spatial limitations of armament. In this paper, for automatic CTA guns a rotating chamber mechanism is designed based on parallel index concept. Via dynamic simulations it proves capable of smooth operation even at as high a firing rate as 200spm. Subsequently, motor controllers are synthesized to drive the chamber at any constant speed and also to control positions in the presence of large disturbances caused by the intermittently-rotating load. It is remarkable that we successfully adopted a disturbance observer to treat disturbances only with a moderate bandwidth of the closed-loop system.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.52 no.4
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• pp.189-197
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• 2003

The problem of designing a parallel feedforward compensator (PFC) is considered for a class of non-square linear systems such that the closed-loop system is strictly passive. If a given square system has (vector) relative degree one and is weakly minimum phase, the system can be rendered passive by a state feedback. However, when the system states are not always measurable and the given output is considered, passivation (i.e. rendering passive) of a non-minimum phase system or a system with high relative degree cannot be achieved by any other methodologies except by using a PFC. To passivate a non-square system we first determine a squaring gain matrix and design a PFC such that the composite system has relative degree one and is minimum phase. Then the system is rendered strictly passvie by a static output feedback law. Necessary and sufficient conditions for the existence of the PFC and the squaring gain matrix are given by the static output feedback formulation, which enables to utilize linear matrix inequality (LMI). As an application of the scheme, an alternative way of replacing the role of velocity measurements is provided for the PD-control law of a convey-crane system.

• Journal of the Korean Institute of Intelligent Systems
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• v.15 no.3
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• pp.324-329
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• 2005

In this paper, a robust $H\infty$ stabilization problem to a uncertain discrete-time nonlinear systems with time-delay via fuzzy static output feedback is investigated. The Takagj-Sugeno (T-S) fuzzy model is employed to represent an uncertain nonlinear system with time-delayed state. Then, the parallel distributed compensation technique is used for designing of the robust fuzzy controller. Using a single Lyapunov function, the globally asymptotic stability and disturbance attenuation of the closed-loop fuzzy control system are discussed. Sufficient conditions for the existence of robust $H\infty$ controllers are given in terms of linear matrix inequalities via similarity transform and congruence transform technique. We have shown the effectiveness and feasibility of the proposed method through the simulation.

• Journal of the Korean Institute of Telematics and Electronics
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• v.17 no.5
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• pp.36-42
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• 1980

In this study, multi-microprocessors system in which slave microprocessor is conrlected with master microprocessor bus through the DMA controller is designed by the use of four 8085 CPU. A high degree of processing efficiency could be obtained by making this system work parallel processing. The result of measuring relat ions bet ween working microproressor and system throughput was 70-80 percents lower than ideal value Master microprocessor takes charge of resource allocation and scheduling, common memory assigns communication between microprocessors and a store of common data. The met hod of detecting Pa rallelism from source Program composed by series is also suggested.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.2C
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• pp.25-30
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• 2005

Turbo code is popularly used for the reliable communication in the presence of burst errors. Even if it shows good error performance near to the Shannon limits, it requires a large amount of memories and exhibits long latency. This paper proposes an architecture for the low power implementation of the Turbo decoder adopting the Max-Log-Map algorithm. In the proposed design, two SISO decoders are designed to operate in parallel, and a novel interleaver is designed to prevent the collision of memory accesses by two SISO decoders. Experimental results show that power consumption has been reduced by about 40% in the proposed decoder compared to previous Turbo decoders. The area overhead due to the additional interleaver controller is negligible.

• The Transactions of the Korean Institute of Power Electronics
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• v.26 no.1
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• pp.53-58
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• 2021

Operation of the interleaved Boost PFC converter in Critical Conduction Mode (CrM) shows the advantages of high efficiency and good EMI characteristics owing to the valley switching of FET. However, when it is designed for a highly pulsating load, operation at a relatively high frequency is inevitable at non-pulsating typical load condition, resulting in efficiency degradation. Moreover, the physical size of the inductor becomes problematic because of the nature of the CrM operation, where the inductor peak current is about two times the inductor average current, thereby requiring high DC-bias characteristics, which is worse when the output power is high. In this study, a new parallel driving method of two sets of interleaved boost PFC converters for highly pulsating high-power application is proposed. The proposed method does not require any additional load-sharing controller, resulting in high efficiency and smaller inductor size.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.11
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• pp.24-32
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• 2002

In this paper we implemented various image processing filtering using the format converter. This design method is based on realized the large processor-per-pixel array by integrated circuit technology. These two types of integrated structure are can be classify associative parallel processor and parallel process DRAM(or SRAM) cell. Layout pitch of one-bit-wide logic is identical memory cell pitch to array high density PEs in integrate structure. This format converter design has control path implementation efficiently, and can be utilize the high technology without complicated controller hardware. Sequence of array instruction are generated by host computer before process start, and instructions are saved on unit controller. Host computer is executed the pixel-parallel operation starting at saved instructions after processing start. As a result, we obtained three result that 1)simple smoothing suppresses higher spatial frequencies, reducing noise but also blurring edges, 2) a smoothing and segmentation process reduces noise while preserving sharp edges, and 3) median filtering, like smoothing and segmentation, may be applied to reduce image noise. Median filtering eliminates spikes while maintaining sharp edges and preserving monotonic variations in pixel values.