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Design of a Low-Power Turbo Decoder Using Parallel SISO Decoders  

Lee, Hee-Jin (서강대학교 전자공학과 CAD & Embedded System 연구실)
Hwang, Sun-Young (서강대학교 전자공학과 CAD & Embedded System 연구실)
Publication Information
The Journal of Korean Institute of Communications and Information Sciences / v.30, no.2C, 2005 , pp. 25-30 More about this Journal
Abstract
Turbo code is popularly used for the reliable communication in the presence of burst errors. Even if it shows good error performance near to the Shannon limits, it requires a large amount of memories and exhibits long latency. This paper proposes an architecture for the low power implementation of the Turbo decoder adopting the Max-Log-Map algorithm. In the proposed design, two SISO decoders are designed to operate in parallel, and a novel interleaver is designed to prevent the collision of memory accesses by two SISO decoders. Experimental results show that power consumption has been reduced by about 40% in the proposed decoder compared to previous Turbo decoders. The area overhead due to the additional interleaver controller is negligible.
Keywords
터보 복호기;저전력 설계;
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