• The Transactions of the Korean Institute of Power Electronics
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• v.12 no.5
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• pp.400-408
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• 2007

In this paper, development of the 8kW parallel module converter is presented. For a effective configuration of FB-PWM converter, this paper proposes 4-parallel operation of 2 kw-module. FB converter of 2-kW module is controlled by phase shut PWM and in order to achieve ZVZCS, the simple auxiliary circuit is applied in secondary side. In order to achieve ZCS, control logic for auxiliary circuit operation is designed to reset the primary current during free-wheeling period. For output current sharing of 4-modules, the charge control is employed. The charge control logic is designed with phase shift PWM logic. Voltage controller is implemented by using DSP(TMS320LF2406) with A/D conversion data of the output current and voltage of each module. The developed converter is installed in PCU(Power Conditioning Unit) for HSG(High Speed Generator) in a vehicle and health monitoring system is implemented for vehicle operation test. Finally, performance of the developed converter is proved under practical operation of HSG.

• Journal of Power Electronics
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• v.11 no.6
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• pp.870-879
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• 2011

Regulated peak power tracking (RPPT) systems such as the series structure and the series-parallel structures are commonly used in satellite space power systems. However, these structures process the solar array power or the battery power to the load through two cascaded regulators during one orbit cycle, which reduces the energy transfer efficiency. Also the battery charging time is increased due to placement of converter between the battery and the solar array. In this paper a parallel structure has been proposed which can improve the energy transfer efficiency and the battery charging time for satellite space power RPPT systems. An analogue controller is used to control all of the required functions, such as load voltage regulation and solar array stabilization with maximum power point tracking (MPPT). In order to compare the system efficiency and the battery charging efficiency of the proposed structure with those of a series (conventional) structure and a simplified series-parallel structure, simulations are performed and the results are analyzed using a loss analysis model. The proposed structure charges the battery more quickly when compared to the other two structures. Also the efficiency of the proposed structure has been improved under different modes of solar array operation when compared with the other two structures. To verify the system, experiments are carried out under different modes of solar array operation, including PPT charge, battery discharge, and eclipse and trickle charge.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.140-150
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• 2006

In this paper, we present a new hardware architecture for testing various cores embedded in SoC. The conventional solutions need much testing time since only one core is tested at single test period. To enhance this, S-TAM, a novel test architecture, and its controller which enable parallel testing of various cores are proposed. S-TAM supports bus sharing to broadcast testing and cores to be tested are selected by using it. In addition, S-TAM controller enables the effective SoC test by simultaneous controlling the various test cores which are based on the different test architectures like IEEE 1149.1 and IEEE 1500.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.3
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• pp.587-594
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• 2005

In the paper, after we propose a viterbi decoder which has multiple buffering and parallel processing decoding scheme through expanding time-divided imput signal, and map a FPGA, we implement a channel coding system together with PC-based software. Continuous input signal is buffered as order of decoding length and is parallel decoded using a high speed cell for viterbi decoding. Output data rate increases linearly with the cell formed the viterbi decoder, and flexible operation can be satisfied by programming controller and modifying input buffer. The tell for viterbi decoder consists of HD block for calculating hamming distance, CM block for calculating value in each state, TB block for trace-back operation, and LIFO. The implemented cell of viterbi decoder used 351 LAB(Logic Arrary Block) and stably operated in maximum 139MHz in APEX20KC EP20K600CB652-7 FPGA of ALTERA. The whole viterbi decoder including viterbi decoding cells, input/output buffers, and a controller occupied the hardware resource of $23\%$ and has the output data rate of 1Gbps.

• Journal of Navigation and Port Research
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• v.33 no.5
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• pp.323-330
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• 2009

We have been developing an underwater robot for harbour construction using a parallel mechanism The robot is attached to the rope of a crane, which curries a large stone into the undersea The robot's yaw and pitch are controlled by hydraulic cylinders but its roll is uncontrollable. We mount propellers in both side of the robot to generate the roll motion This paper studies on the control for the roll motion of a underwater robot. A gyro-sensor is used to measure the angle in a roll motion We develop the dynamic model to describe the robot's roll motion by a second order non-linear system and identify the model parameters by recursive least square and adaptive identifier. PD control, recursive model based control and adaptive model based control are applied with the dynamic model which computes the control input to compensate disturbances. This paper introduces the underwater robot system and presents the simulated and experimental results of the proposed controller.

• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.1
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• pp.81-89
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• 2012

Commonly used horizontal-axis wind turbines (HAWT) have the following structure: two or three blades, a nacelle which contains power converting equipments, generators, and a tower which supports the nacelle. The generated power is transmitted from the nacelle to the ground. Due to this structure, the power transmission lines are twisted when the nacelle is yawing. Thus, slip ring or additional yaw control mechanism is required. We propose a new structure of HAWT which is free of this transmission line problem. Moreover, the size of inverter can be reduced since two generators are connected in parallel in our mechanism so that power is distributed. A controller for yawing is developed so that it works in harmony with the controller for power generation. A MPPT (Maximum Power Point tracking) algorithm is implemented for the proposed system and efficiency of the system is validated by simulation.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.1
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• pp.51-65
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• 2002

This paper presents a design method of the neural network-based controller using an indirect adaptive control method to deal with an intelligent control for chaotic nonlinear systems. The proposed control method includes the identification and control Process for chaotic nonlinear systems. The identification process for chaotic nonlinear systems is an off-line process which utilizes the serial-parallel structure of multilayer neural networks and simple state space neural networks. The control process is an on-line process which uses the trained neural networks as the system model. An error back-propagation method was used for training of identification and control for chaotic nonlinear systems. The performance of the proposed neural network controller was evaluated by application to the Duffing equation and the Lorenz equation, and the proposed controller was compared with other neural network-based controllers by computer simulations.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.6
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• pp.1409-1418
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• 1998

The recent audio CODEC(Coding/Decoding) algorithms are complex of several coding techniques, and can be divided into DSP tasks, controller tasks and mixed tasks. The traditional DSP processor has been designed for fast processing of DSP tasks only, but not for controller and mixed tasks. This paper presents a new architecture that achieves high throughput on both controller and mixed tasks of such algorithms while maintaining high performance for DSP tasks. The proposed processor, YSP-3, operates four algorithms while maintaining high performance for DSP tasks. The proposed processor, YSP-3, operates functional units (Multiplier, two ALUs, Load/Store Unit) in parallel via 4-issue super-scalar instruction structure. The performance evaluation of YSP-3 has been done through the implementation of the several DSP algorithms and the part of the AC-3 decoding algorithms.

• Journal of the Korean Institute of Intelligent Systems
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• v.13 no.6
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• pp.667-672
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• 2003

In this paper, we propose a systematic method for intelligent digital redesign of a fuzzy-model-based controller for continuous-time nonlinear dynamical systems which may also contain uncertainties. The continuous-time uncertain TS fuzzy model is first constructed to represent the uncertain nonlinear systems. An extended parallel distributed compensation(EPDC) technique is then used to design a fuzzy-model-based controller for both stabilization and tracking. The designed continuous-time controller is then converted to an equivalent discrete-time controller by using an integrated intelligent digital redesign method. This new design technique provides a systematic and effective framework for integration of the fuzzy-model-based control theory and the advanced digital redesign technique for nonlinear dynamical systems with uncertainties. Finally, The single link flexible-joint robot arm is used as an illustrative example to show the effectiveness and the feasibility of the developed design method.

• Journal of Power Electronics
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• v.16 no.1
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• pp.297-309
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• 2016

Grid-connected inverters (GCIs) with an LCL output filter have the ability of attenuating high-frequency (HF) switching ripples. However, by using only grid-current control, the system is prone to resonances if it is not properly damped, and the current distortion is amplified significantly under highly distorted grid conditions. This paper proposes a synchronous reference frame equivalent proportional-integral (SRF-EPI) controller in the αβ stationary frame using the parallel virtual resistance-based active damping (PVR-AD) strategy for grid-interfaced distributed generation (DG) systems to suppress LCL resonance. Although both a proportional-resonant (PR) controller in the αβ stationary frame and a PI controller in the dq synchronous frame achieve zero steady-state error, the amplitude- and phase-frequency characteristics differ greatly from each other except for the reference tracking at the fundamental frequency. Therefore, an accurate SRF-EPI controller in the αβ stationary frame is established to achieve precise tracking accuracy. Moreover, the robustness, the harmonic rejection capability, and the influence of the control delay are investigated by the Nyquist stability criterion when the PVR-based AD method is adopted. Furthermore, grid voltage feed-forward and multiple PR controllers are integrated into the current loop to mitigate the current distortion introduced by the grid background distortion. In addition, the parameters design guidelines are presented to show the effectiveness of the proposed strategy. Finally, simulation and experimental results are provided to validate the feasibility of the proposed control approach.