• Water for future
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• v.20 no.3
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• pp.229-235
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• 1987

The purpose of this study is to estimate the parameters of linear reservoir models in order to derive the Instantaneous unit hydrograph from a given small experimental watershed. The linear reservoir model is a conceptual model, consisting of cascade or parallel equal linear reservoirs, preceded by a linear channel which involved Nash, SLR(single linear reservoir) and 2-PLR(two-parallel linear Reservoir) model. the Nash model have two parameters N and K, single linear reseroir has one parameter $K_I$ and two-parallel linear reservoirs have two parameters $K_1,\;K_2$; where N denote the number of reservoirs and K is the storage coefficient of each reservoirs.

• Proceedings of the Korea Water Resources Association Conference
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• 1987.07a
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• pp.151-158
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• 1987

The purpose of thes study is to estimate the parameters of linear reservoir models in order to derive the instantaneous unit hydrograph from a given small experimental watershed. The linear reservoir model is a conceptual model, consisting of cascade or parallel equal linear reservoirs, preceded by a linear channel which involved NASH, SLR(single linear reservoir)and 2-PLR(two-parallel linear reservoir)model. The NASH model have two parameters N and K, single linear reservoir has one parameter K1 and two-parallel linear reservoirs have two parameters K1, K2;where N denote the number of reservoirs and K is the storage coefficient of each reservoirs.

• 한국전산유체공학회:학술대회논문집
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• 2006.05a
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• pp.395-397
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• 2006

Air interlacing serves to protect the yarn against damage, strengthens inter-filament compactness or cohesion, and ensures fabric consistency. The air interlacing nozzle is used to introduce intermittent nips to a filament yarn so as to improve its performance in textile processing. The effect of various interlacing nozzle geometries on the interlacing process was studied. The geometries of interlacing nozzles with single or multiple air inlets located across the width of yarn channels are investigated. The basis case is the yarn channel, with a perpendicular main air inlet in the middle. Other cases have main air inlets, slightly inclined double sub air inlets, The yarn channel cross sectional shapes are either semicircular or rectangular shapes. The compressed impinging jet from the main air inlet hole hits the opposing bottom wall of the yarn channel, is divided into two branches, joins with the compressed air coming out from sub air inlet at the bottom and creates two free jets at both ends of the yarn channel. The compressed air movement in the cross-section consists of two opposing directional vortices. The CFD-FASTRAN flow parallel solver was used to perform steady simulations of impinging jet flow inside of the interlace nozzles. The vortical structure and the flow pattern such as pressure contour, particle traces, velocity vector plots inside of interlace nozzle geometry are discussed in this pater.

• Korean Journal of Air-Conditioning and Refrigeration Engineering
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• v.29 no.8
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• pp.401-407
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• 2017

The effect of different rib geometries such as V-shaped continuous (case A), parallel broken (case B), and V-shaped broken (case C) ribs on local heat transfer distributions and pressure drops in a divergent channel with $30^{\circ}$ inclined ribs on one wall or two walls was investigated for Reynolds numbers from 22,000 to 75,000. Top and bottom walls were insulated; two side walls were uniformly heated in the divergent channel. Heated walls were composed of 10 isolated coper sections and length-to-outlet hydraulic diameter ratio of 10. Rib height-to-outlet hydraulic diameter ratio was 0.1, and rib pitch-to-height ratio equaled 10. Results revealed that V-shaped continuous rib (case A) produced approximately 1.4 times higher average Nussselt number than in the parallel broken rib (case B), and V-shaped broken rib (case C) in the channel with two ribbed walls at Re = 54,000.

• Journal of Magnetics
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• v.22 no.2
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• pp.238-243
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• 2017

In this research, we report the preliminary results of an insertional type parallel transmission (pTx) array that has 7-elements that are placed in the space above a patient table as a transmit (Tx) coil to give an RF transmission ($B_1{^+}$) field for the body object of a 3 Tesla (T) MRI system. In previous research, we have tried to compare the performances of different coil elements and array geometries for a pTx body image. Based on these results, we attempt to obtain a human image with the proposed pTx array. Through the simulation and experimental results, we introduce a possible structure of multi-channel Tx array and verify the utility of a multi-channel Tx body image using $B_1{^+}$ shimming. The insertional pTx array, combined with a receiver (Rx) array coil, provides an enhanced $B_1{^+}$ field homogeneity in a large ROI image as a result of $B_1{^+}$ shimming applied over the full body size object. Through this research, we hope to determine the usefulness of the proposed insertional type RF coil combination for 3 T body imaging.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.37 no.1
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• pp.54-65
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• 2000

We propose a parallel acquisition scheme using antenna arrays for initial acquisition of direct-sequence spread-spectrum (DS-SS) signals. The proposed parallel scheme can lower substantially the range of detectable signal-to-noise ratio (SNR) as compared to the conventional parallel scheme with a single antenna. The proposed scheme uses the sum of the independent decision samples from antenna arrays corresponding to an identical subsequence of the pseudonoise (PN) code as a decision variable. We derive the probabilities of detection, missing, and false alarm under an additive white Gaussian noise (AWGN) channel and a flat Rayleigh fading channel. Using these, we get the mean acquisition time of the proposed scheme. From numerical results, we see that the acquisition performance becomes improved continually as the number of antennas increases.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.6
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• pp.25-34
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• 2000

This paper describes design of a 250-Mbps 10-channel optical receiver array for parallel optical interconnection with the general-purpose CMOS technology The optical receiver is one of the most important building blocks to determine performance of the parallel optical interconnection system. The chip in CMOS technology makes it possible to implement the cost-effective system also. Each data channel consists of analog front-end including the integrated photo-detector and amplifier chain, digital block with D-FF and off-chip driver. In addition, the chip includes PLL (Phase-Lock Loop) for synchronous data recovery. The chip was fabricated in a 0.65-${\mu}{\textrm}{m}$ 2-poly, 2-metal CMOS technology. Power dissipation of each channel is 330㎽ for $\pm$2.5V supply.

• Journal of Advanced Navigation Technology
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• v.21 no.5
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• pp.485-490
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• 2017

In this paper, we propose a technique for high speed removal of sea-fog using a graphic processor. This technique uses a host processor(CPU) and several graphics processors(GPU) capable of parallel processing to remove sea-fog from the input image. In the process of removing sea-fog, the dark channel extraction, the maximum brightness channel extraction, and the calculation of the transmission are performed by the host processor, and the process of refining the transmission by applying the bidirectional filter is performed in parallel through the graphic processor. To verify the proposed parallel processing method, three NVIDIA GTX 1070 GPUs were used to construct the verification environment. As a result, it takes about 140ms when implemented with one graphics processor, and 26ms when implemented using OpenMP and multiple GPGPUs. The proposed a parallel processing algorithm based on the graphics processor unit can be used for safe navigation, port control and monitoring system.

• Proceedings of the IEEK Conference
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• 2003.07c
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• pp.2609-2612
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• 2003

This paper describes a 64 channel signal generator/analyzer module that is useful for verification and testing of digital circuits. It can perform logic analyzer function and signal generator function at the same time. The 64 Channel module is implemented with single FPGA chip for miniaturization, and an USB interface is used to increase portability of the module. Multiple modules can be used in parallel for the verification of large scale circuits. Moreover, since the module is implemented as a PC based system, one can configure convenient GUI(Graphic User Interface) environment.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1263-1265
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• 2007

The electrical characteristics of low temperature poly-Si (LTPS) thin-film transistors (TFT) with channel parallel and perpendicular to the direction of lateral growth were studied. The poly-Si film was crystallized using sequential lateral solidification (SLS) laser crystallization technique. The channel orientation dependent turn-on characteristics were investigated by using gated-diodes and capacitance-voltage measurements