• Title/Summary/Keyword: Paper chip

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Diagnostic Paper Chip for Reliable Quantitative Detection of Albumin using Retention Factor (체류 인자를 이용한, 알부민의 정량 분석용 종이 칩)

  • Jeong, Seong-Geun;Lee, Sang-Ho;Lee, Chang-Soo
    • KSBB Journal
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    • v.28 no.4
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    • pp.254-259
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    • 2013
  • Herein we present a diagnostic paper chip that can quantitatively detect albumin without external electronic reader and dispensing apparatus. We fabricated a diagnostic paper chip device by printing wax barrier on the paper and wicking it with citrate buffer and tetrabromophenol blue to detect albumin in sample solution. The paper chip is so simple that we dropped a sample solution at sample pad and measure the ratio of two travel distances of the sample solvent and albumin under the name of retention factor. Our result confirmed that the retention factor was constant in the samples with same concentration of albumin and useful determinant for the measurement of albumin concentration. The paper chip is affordable and equipment-free, and close to ideal point-of-care test in accordance with the assured criteria, outlined by the World Health Organization. We assume that this diagnostic paper chip will expand the concept of colorimetric determination and provide a inexpensive diagnostic method to aging society and developing country.

Realization of one chip for opto-couplers in driving circuit of electric valve (전동밸브의 구동회로에서 Opto-Coupler들의 one chip화 구현)

  • 정원채
    • Proceedings of the IEEK Conference
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    • 2001.06e
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    • pp.181-184
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    • 2001
  • This paper has been studied driving circuits in electrical valves. Also in this paper, opto-couplers of driving circuit are replaced with digital one chip of Altera company. Designs in order to realization of one chip are carried out with Altera Max Plus II. For compact size and light weight, the realization with one chip is necessary in the electrical valves. This paper has designed and presented the digital schemetic circuits, finally the driving circuits are sucessfully operated with the designed chip and showed the saving of area in the driving circuits of electric valves.

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Development of Pattern Classifying System for cDNA-Chip Image Data Analysis

  • Kim, Dae-Wook;Park, Chang-Hyun;Sim, Kwee-Bo
    • 제어로봇시스템학회:학술대회논문집
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    • 2005.06a
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    • pp.838-841
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    • 2005
  • DNA Chip is able to show DNA-Data that includes diseases of sample to User by using complementary characters of DNA. So this paper studied Neural Network algorithm for Image data processing of DNA-chip. DNA chip outputs image data of colors and intensities of lights when some sample DNA is putted on DNA-chip, and we can classify pattern of these image data on user pc environment through artificial neural network and some of image processing algorithms. Ultimate aim is developing of pattern classifying algorithm, simulating this algorithm and so getting information of one's diseases through applying this algorithm. Namely, this paper study artificial neural network algorithm for classifying pattern of image data that is obtained from DNA-chip. And, by using histogram, gradient edge, ANN and learning algorithm, we can analyze and classifying pattern of this DNA-chip image data. so we are able to monitor, and simulating this algorithm.

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Performance Evaluation of Chip Breaker Utilizing Neural Network (신경망기법에 의한 칩브레이커의 성능평가)

  • Kim, Hong-Gyoo;Sim, Jae-Hyung
    • Transactions of the Korean Society of Machine Tool Engineers
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    • v.16 no.3
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    • pp.64-74
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    • 2007
  • The continuous chip in turning operation deteriorates precision of workpiece and causes a hazardous condition to operator. Thus the chip form control becomes a very important task for reliable machining process. So, grooved chip breaker is widely used to obtain reliable discontinuous chip. However, developing new cutting insert having chip breaker takes long time and needs lots of research expense due to a couple of processes such as forming, sintering, grinding and coating of product and many different evaluation tests. In this paper, performance of commercial chip breaker is evaluated with neural network which is learned with a back propagation algorithm. For the evaluation, several important elements(depth of cut, land, breadth, radius) which directly influence the chip formation were chosen among commercial chip breakers and were used as input values of neural network. With the results of these input values, the performance evaluation method was developed and applied that method to the commercial tools.

Control if Chip From by Adjusting Feed-rate (이송량 조정에 의한 칩의 형태 제어)

  • 전재억;심재형;백인환
    • Proceedings of the Korean Society of Precision Engineering Conference
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    • 1997.04a
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    • pp.993-997
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    • 1997
  • The continuous chip depresses the accuracy of workpieces and promotes the wear of machine tools and hunts operators. So chip control os a major problem in turning process. In this paper, a method of chip identification is develope by pyrometer. The identifier is applied in real-time control of chip pattern with adjusting feedrate.

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Studies on Flip Chip Underfill Process by using Molding System (몰딩공정을 응용한 플립칩 언더필 연구)

  • 한세진;정철화;차재원;서화일;김광선
    • Journal of the Semiconductor & Display Technology
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    • v.1 no.1
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    • pp.29-33
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    • 2002
  • In the flip-chip process, the problem like electric defect or fatigue crack caused by the difference of CTE, between chip and substrate board had occurred. Underfill of flip chip to overcome this defects is noticed as important work developing in whole reliability of chip by protecting the chip against the external shock. In this paper, we introduce the underfill methods using mold and plunge and improvement of process and reliability, and the advantage which can be taken from embodiment of device.

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A Bus Data Compression Method on a Phase-Based On-Chip Bus

  • Lee, Jae-Sung
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.12 no.2
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    • pp.117-126
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    • 2012
  • This paper provides a method for compression transmission of on-chip bus data. As the data traffic on on-chip buses is rapidly increasing with enlarged video resolutions, many video processor chips suffer from a lack of bus bandwidth and their IP cores have to wait for a longer time to get a bus grant. In multimedia data such as images and video, the adjacent data signals very often have little or no difference between them. Taking advantage of this point, this paper develops a simple bus data compression method to improve the chip performance and presents its hardware implementation. The method is applied to a Video Codec - 1 (VC-1) decoder chip and reduces the processing time of one macro-block by 13.6% and 10.3% for SD and HD videos, respectively

Digital Hearing Aid DSP Chip Parameter Fitting Optimization (디지털 보청기 DSP Chip 파라미터 적합 최적화)

  • Jarng Soon-Suck
    • Journal of Institute of Control, Robotics and Systems
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    • v.12 no.6
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    • pp.530-538
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    • 2006
  • DSP chip parameters of a digital hearing aid (HA) should be optimally selected or fitted for hearing impaired persons. The more precise parameter fitting guarantees the better compensation of the hearing loss (HL). Digital HAs adopt DSP chips for more precise fitting of various HL threshold curve patterns. A specific DSP chip such as Gennum GB3211 was designed and manufactured in order to match up to about 4.7 billion different possible HL cases with combination of 7 limited parameters. This paper deals with a digital HA fitting program which is developed for optimal fitting of GB3211 DSP chip parameters. The fitting program has completed features from audiogram input to DSP chip interface. The compensation effects of the microphone and the receiver are also included. The paper shows some application examples.

Chip Breaking Prediction in Turning Process Considering Cutting Conditions and Chip Breaker Parameters (절삭조건과 칩브레이커 형상변수를 고려한 선삭 가공시의 칩절단 예측)

  • Choi, Jin-Pil;Lee, Sang-Jo
    • Journal of the Korean Society for Precision Engineering
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    • v.16 no.9
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    • pp.191-199
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    • 1999
  • In the continuous cutting process such as turning operation, chip control is thought very important to achieve the unmanned manufacturing system. The prediction of chip breakage under the given conditions is a substantial element for chip control. In this paper, a systematic approach to know the chip breaking region is represented under the concept of equivalent parameters. to Verify the suggested model, cutting experiments are executed with a commercial type and two other type chip breakers which have modified chip breaker parameters such as land width, groove width and nose radius. predicted chip breaking regions using the 3D cutting model agrees with those obtained from the experiments.

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Performance Analysis for MPEG-4 Video Codec Based on On-Chip Network

  • Chang, June-Young;Kim, Won-Jong;Bae, Young-Hwan;Han, Jin-Ho;Cho, Han-Jin;Jung, Hee-Bum
    • ETRI Journal
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    • v.27 no.5
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    • pp.497-503
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    • 2005
  • In this paper, we present a performance analysis for an MPEG-4 video codec based on the on-chip network communication architecture. The existing on-chip buses of system-on-a-chip (SoC) have some limitation on data traffic bandwidth since a large number of silicon IPs share the bus. An on-chip network is introduced to solve the problem of on-chip buses, in which the concept of a computer network is applied to the communication architecture of SoC. We compared the performance of the MPEG-4 video codec based on the on-chip network and Advanced Micro-controller Bus Architecture (AMBA) on-chip bus. Experimental results show that the performance of the MPEG-4 video codec based on the on-chip network is improved over 50% compared to the design based on a multi-layer AMBA bus.

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