• 제목/요약/키워드: Package printing

검색결과 45건 처리시간 0.021초

선택적 전기화학 3D 프린터 기술 소개 및 PCB 양산공정 적용방식 고찰 (Introduction of Selective Electrochemical Additive Manufacturing Technology and Consideration of Integration Method for PCB Mass Production Process)

  • 김성빈;유봉영
    • 한국표면공학회지
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    • 제54권3호
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    • pp.158-163
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    • 2021
  • Some studies on electrochemical additive manufacturing of metals were summarized in this technical report, and development status of selective electrochemical 3D printing technology was introduced. In order to apply it to the PCB mass production process, essential considerations how to overcome the fundamental problems, such as the sizing, process sequence and PCB process design have been described.

잉크젯 프린팅에서 해상력에 관한 컴퓨터 시뮬레이션 연구 (A Study on the Simulation of the Resolution for Ink-Jet Printing)

  • 이지은;윤종태;구철회
    • 한국인쇄학회지
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    • 제28권1호
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    • pp.51-63
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    • 2010
  • Ink-jet is part of the non impact printing that shooting the ink drop from the nozzle to paper. It is very silence and express good color. There are two types of printing that continuous and drop on demand. But drop on demand process is becoming the mainstream. these days, LCD, PDP is passed more than semiconductor industry. And we expect organic EL, FED as a next display. But product equipment, main component and technology have a gap between an advanced country and us nevertheless physical development. Expecially, previous process part is depended on imports. Ink-jet printing technology that there isn't complicated photo lithography process is attracted, so ink-jet printing resolution is more embossed. But there were not many of ink-jet resolution thesis but ink-jet head or nozzle. Because, to out of the ink from the nozzle is unseeable and hard to experiment. Therefore this thesis was experimented and simulated how can ink-jet printer improved resolution by flow-3d simulation package program.

오프셋 인쇄의 틈새출구에서 공동의 변화에 대한 시뮬레이션 (Computer Simulation for the Cavitation Changes at the Exit of Offset Printing Nip)

  • 윤종태;김윤택;임수만
    • 펄프종이기술
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    • 제46권3호
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    • pp.1-10
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    • 2014
  • Offset paper printing is a promising roll-to-roll technique for color printed materials. Although it is no doubt that understanding ink transfer mechanism in offset printing process is necessary to achieve high printing quality, investing the relationship between inks and substrates at the nip is difficult experimentally due to high printing speed. In this paper, rheological behavior and splitting point of the ink at the nip is studied using package software Ployflow and Flow 3D based on Navier-Stokes equation. Polydimethylsiloxane (PDMS) ink and IGT printability tester were used for an model ink and experiment to compare with that of simulation data, respectively. As a result, higher viscosity at state flow and pressure increased ink transfer due to higher possibility of presence of cavitation at the nip and increase in covering area ratio. These results have shown good agreements with experimental data compared by measuring density of print through.

The Substitution of Inkjet-printed Gold Nanoparticles for Electroplated Gold Films in Electronic Package

  • 장선희;강성구;김동훈
    • 한국재료학회:학술대회논문집
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    • 한국재료학회 2011년도 추계학술발표대회
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    • pp.25.1-25.1
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    • 2011
  • Over the past few decades, metallic nanoparticles (NPs) have been of great interest due to their unique mesoscopic properties which distinguish them from those of bulk metals; such as lowered melting points, greater versatility that allows for more ease of processability, and tunable optical and mechanical properties. Due to these unique properties, potential opportunities are seen for applications that incorporate nanomaterials into optical and electronic devices. Specifically, the development of metallic NPs has gained significant interest within the electronics field and technological community as a whole. In this study, gold (Au) pads for surface finish in electronic package were developed by inkjet printing of Au NPs. The microstructures of inkjet-printed Au film were investigated by various thermal treatment conditions. The film showed the grain growth as well as bonding between NPs. The film became denser with pore elimination when NPs were sintered under gas flows of $N_2$-bubbled through formic acid ($FA/N_2$) and $N_2$, which resulted in improvement of electrical conductance. The resistivity of film was 4.79 ${\mu}{\Omega}$-cm, about twice of bulk value. From organic anlayses of FTIR, Raman spectroscopy, and TGA, the amount of organic residue in the film was 0.43% which meant considerable removal of the solvent or organic capping molecules. The solder ball shear test was adopted for solderability and shear strength value was 820 gf (1 gf=9.81 mN) on average. This shear strength is good enough to substitute the inkjet-printed Au nanoparticulate film for electroplating in electronic package.

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Glass Remote Phosphor 구조를 갖는 백색 LED 패키지의 형광체 함량과 열처리 온도 최적화 (Optimization of Phosphor Contents and Heat-treatment Temperature in White LED Package with Glass Remote Phosphor Structure)

  • 정희석;홍석기;염정덕
    • 조명전기설비학회논문지
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    • 제30권3호
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    • pp.30-38
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    • 2016
  • In this research, a 6W white LED package with a Glass Remote Phosphor was developed to improve the life of an LED package. The Glass Remote Phosphor was fabricated by the Phosphor in Glass (PiG) method, wherein phosphor YAG:Ce was mixed with glass frit and then heat treated. A paste with 75wt.% of a phosphor substance and 25wt.% glass frit was coated on a glass substrate two times using the screen-printing technique and heat-treated at $800^{\circ}C$ ; this structure gave a luminous efficacy of 136.1lm/W, color rendering index of 74Ra, and color temperature of 5,342K, thus satisfying the requirements as a light source for lighting. Moreover, an IES LM-80 accelerated life test was conducted on the same LED package for 6,000h in order to estimate the L70 lifetime based on IES TM-21. The results showed guaranteed lifetimes of 213,000h at $55^{\circ}C$, 245,000h at $85^{\circ}C$, and 209,000h at $95^{\circ}C$.

고전력 LED용 적층형 LTCC 패키징의 ZnO 조성 변화가 방열 특성에 미치는 영향 (Effects of ZnO Composition on the Thermal Emission Properties for LTCC Type of High Power LED Package)

  • 김우정;김형수;신대규;이희철
    • 마이크로전자및패키징학회지
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    • 제19권4호
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    • pp.79-83
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    • 2012
  • 신뢰성이 우수하며, 소형화가 가능하고, 우수한 열전도도의 은 전극을 이용할 수 있는 LTCC (Low temperature co-fired ceramic) 패키징은 환경 및 열에 약한 플라스틱 패키징을 대체할 것으로 기대받고 있다. 현재 LTCC 패키징의 원료 분말로는 주로 $Al_2O_3$을 사용하는데, 본 연구에서는 $Al_2O_3$보다 열전도도가 2배 우수한 ZnO을 일부 첨가 또는 대체한 조성 변화를 통하여 패키징의 열 특성 변화에 대해 연구하였다. 소량의 ZnO를 첨가하여 열전도도가 최대 25%까지 상승하는 결과가 나타났으며, 이 결과로 LED 수명이 증가할 것으로 예상된다. ANSYS 시뮬레이션 결과 열 유속의 값이 ZnO가 첨가된 경우 최대 56% 증가함을 확인할 수 있었다. 실제 LED 패키징을 제작하여 측정한 결과도 ZnO를 첨가한 LTCC 패키징은 $Al_2O_3$로만 이루어진 패키징보다 열저항이 최대 14.9% 감소하였다.

형광체 코팅에 따른 Remote Phosphor 구조의 백색 LED 패키지 특성 평가 (Evaluation of White LED Package Characteristics in Remote Phosphor Structure Depending on Phosphor Coatings)

  • 정희석;이정근;강한림;황명근;이미재;김진호;채유진;이영식
    • 한국전기전자재료학회논문지
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    • 제26권4호
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    • pp.330-334
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    • 2013
  • We developed a package of remote phosphor structure having blue LED chips and phosphors physically separated, and the characteristics were evaluated according to different classifications of phosphor coatings. Remote phosphor was produced by screen printing coating on glass substrate with phosphor content rated paste and heat treatment. After mounting Remote phosphor, which has been classified according to number of coatings, on top of blue LED chips, luminous flux, luminous efficacy, CCT and CRI were measured. The measurement results showed the most suitable characteristics of white LED package as a general light source when the content rate of phosphor in Remote phosphor was 80 wt.% with 3 layers of coatings and thickness over $12{\mu}m$.

BGA to CSP to Flip Chip-Manufacturing Issues

  • Caswell, Greg;Partridge, Julian
    • 마이크로전자및패키징학회지
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    • 제8권2호
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    • pp.37-42
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    • 2001
  • The BGA package has been the area array package of choice for several years. Recently, the transition has been to finer pitch configurations called Chip Scale Packages (CSP). Several of these package types are available at 0.5 mm pitch. requiring surface mount assemblers to evaluate and optimize various elements of the assembly process. This presentation describes the issues associated with making the transition from BGA to CSP assembly. Areas addressed will include the accuracy of pick and place equipment, printed wiring board lines and spaces, PWB vias, in-circuit test issues, solder paste printing, moisture related factors, rework and reliability. The transition to 0.5 mm pitch requires careful evaluation of the board design, solder paste selection, stencil design and component placement accuracy. At this pitch, ball and board pad diameters can be as small as 0.25 mm and 0.20 mm respectively. Drilled interstitial vias are no longer possible and higher ball count packages require micro-via board technology. The transition to CSP requires careful evaluation of these issues. Normal paste registration and BGA component tolerances can no longer achieve the required process levels and higher accuracy pick and place machines need to be implemented. This presentation will examine the optimization of these critical assembly operations, contrast the challenges at 0.5 mm and also look at the continuation of the process to incorporate smaller pitch flip chip devices.

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BGA to CSP to Flip Chip - Manufacturing Issues

  • Caswell, Greg;Partridge, Julian
    • 한국마이크로전자및패키징학회:학술대회논문집
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    • 한국마이크로전자및패키징학회 2001년도 Proceedings of 6th International Joint Symposium on Microeletronics and Packaging
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    • pp.27-34
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    • 2001
  • The BGA Package has been the area array package of choice for several rears. Recently, the transition has been to finer pitch configuration called Chip Scale Packages (CSP). Several of these package types are available at 0.5 mm pitch, requiring surface mount assemblers to evaluate and optimize various elements of the assembly process. This presentation describes the issues associated with making the transition from BGA to CSP assembly. Areas addressed will include the accuracy of pick and piece equipment, printed wiring board lines and spaces, PWB vias, in-circuit test issues, solder paste printing, moisture related factors, rework and reliability. The transition to 0.5 mm pitch requires careful evaluation of the board design, solder paste selection, stencil design and component placement accuracy. At this pitch, ball and board pad diameters can be as small as 0.25 mm and 0.20 mm respectively. Drilled interstitial vias are no longer possible and higher ball count packages require micro-via board technology. The transition to CSP requires careful evaluation of these issues. Normal paste registration and BGA component tolerances can no longer achieve the required process levels and higher accuracy pick and place machines need to be implemented. This presentation will examine the optimization of these critical assembly operations, contrast the challenges at 0.5 mm and also look at the continuation of the process to incorporate smaller pitch flip chip devices.

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그라비어에서 잉크 침투의 컴퓨터 시뮬레이션 (The Computer Simulation of Ink Penetration in the Gravure)

  • 윤종태
    • 한국인쇄학회지
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    • 제28권2호
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    • pp.45-56
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    • 2010
  • The computer simulation is presented of gravure ink transferring behavior and penetration to the paper when an gravure roller is used to transfer a printing ink onto a substrate. The three dimensional unsteady ink motion is simulated by Polyflow package software and experimented by IGT gravure printing test machine. The simulation is performed where the flow domain is bounded above by a stress free surface and bounded below by a moving substrate. Specific predictions are made for particular pattern of cells and substrates. Cell size and ink rheological properties are found to be the principal determination of transferring behavior. Simulation is currently restricted to the flow domain beneath the receding meniscus. Both Newtonian and shear thinning inks are considered.