• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2003년도 International Symposium
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• pp.165-172
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• 2003

Wafer-level packaging technology has become established with increase of demands for miniaturizing and realizing lightweight electronic devices evolution. This packaging technology enables the smallest footprint of packaged chip. Various structures and processes has been proposed and manufactured currently, and products taking advantages of wafer-level package come onto the market. The package enables mounting semiconductor chip on print circuit board as is a case with conventional die-level CSP's with BGA solder bumps. Bumping technology is also advancing in both lead-free solder alternative and wafer-level processing such as stencil printing using solder paste. It is known lead-free solder bump formation by stencil printing process tend to form voids in the re-flowed bump. From the result of FEM analysis, it has been found that the strain in solder joints with voids are not always larger than those of without voids. In this paper, characteristics of wafer-level package and effect of void in solder bump on its reliability will be discussed.

• Journal of Welding and Joining
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• 제18권2호
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• pp.222-222
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• 2000

PBGA(Plastic Ball Grid Array) is composed of some materials such as PCB(Printed Circuit Board), epoxy molding compound, die attach and so on. Reliability of PBGA package is weak compared with plastic packages. The weak points of reliability are the lower resistance to popcorn cracking, which is induced by moisture absorption in PCB, and the pressure cooker test corrosion, which is the basic problem due to the material characteristics of PCB. Introducing the PCB baking and the plasma treatment cleared the popcorn cracking phenomenon. The PCB baking and plasma treatment reduced the epoxy void by eliminating the source of moisture vaporization during the epoxy curing and enhanced the adhesion between PCB and epoxy. Also, plasma treatment enhanced the wettability of epoxy on PCB. The problem of corrosion is cleared using multi-functional epoxy. This type of EMC(Epoxy Molding Compound) is recommended in package using PCB as a substrate. (Received November 19, 1999)

• Journal of Welding and Joining
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• 제18권2호
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• pp.95-99
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• 2000

PBGA(Plastic Ball Grid Array) is composed of some materials such as PCB(Printed Circuit Board), epoxy molding compound, die attach and so on. Reliability of PBGA package is weak compared with plastic packages. The weak points of reliability are the lower resistance to popcorn cracking, which is induced by moisture absorption in PCB, and the pressure cooker test corrosion, which is the basic problem due to the material characteristics of PCB. Introducing the PCB banking and the plasma treatment cleared the popcorn cracking phenomenon. The PCB banking and plasma treatment reduced the epoxy void by eliminating the source of moisture vaporization during the epoxy curing and enhanced the adhesion between PCB and epoxy. Also, plasma treatment enhanced the wettability of epoxy on PCB. The problem of corrosion is cleared using multi-functional epoxy. This type of EMC(Epoxy Molding Compound) is recommended in package using PCB as a substrate.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2009년도 제40회 하계학술대회
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• pp.1511_1512
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• 2009

This paper presents a polarization switching antenna integrated with silicon RF MEMS SPDT switches in the form of a package. A low-loss quartz substrate made of SoQ (silicon-on-quartz) bonding is used as a dielectric material of the patch antenna, as well as a packaging lid substrate of RF MEMS switches. The packaging/antenna substrate is bonded with the bottom substrate including feeding lines and RF MEMS switches by BCB adhesive bonding, and RF energy is transmitted from signal lines to antenna by slot coupling. Through this approach, fabrication complexity and degradation of RF performances of the antenna due to the parasitic effects, which are all caused from the packaging methods, can be reduced. This structure is expected to be used as a platform for reconfigurable antennas with RF MEMS tunable components. A linear polarization switching antenna operating at 19 GHz is manufactured based on the proposed method, and the fabrication process is carefully described. The s-parameters of the fabricated antenna at each state are measured to evaluate the antenna performance.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2000년도 Proceedings of 5th International Joint Symposium on Microeletronics and Packaging
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• pp.43-55
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• 2000

In traditional electronic packages the die and the substrate are interconnected with fine wire. Wire bonding technology is limited to bond pads around the peripheral of the die. As the demand for I/O increases, there will be limitations with wire bonding technology. Flip chip technology eliminates the need for wire bonding by redistributing the bond pads over the entire surface of the die. Instead of wires, the die is attached to the substrate utilizing a direct solder connection. Although several steps and processes are eliminated when utilizing flip chip technology, there are several new problems that must be overcome. The main issue is the mismatch in the coefficient of thermal expansion (CTE) of the silicon die and the substrate. This mismatch will cause premature solder Joint failure. This issue can be compensated for by the use of an underfill material between the die and the substrate. Underfill helps to extend the working life of the device by providing environmental protection and structural integrity. Flux residues may interfere with the flow of underfill encapsulants causing gross solder voids and premature failure of the solder connection. Furthermore, flux residues may chemically react with the underfill polymer causing a change in its mechanical and thermal properties. As flip chip packages decrease in size, cleaning becomes more challenging. While package size continues to decrease, the total number of 1/0 continue to increase. As the I/O increases, the array density of the package increases and as the array density increases, the pitch decreases. If the pitch is decreasing, the standoff is also decreasing. This paper will present the keys to successful flip chip cleaning processes. Process parameters such as time, temperature, solvency, and impingement energy required for successful cleaning will be addressed. Flip chip packages will be cleaned and subjected to JEDEC level 3 testing, followed by accelerated stress testing. The devices will then be analyzed using acoustic microscopy and the results and conclusions reported.

• 마이크로전자및패키징학회지
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• 제6권4호
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• pp.23-33
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• 1999

유한요소법을 이용한 IGBT 3상 풀브릿지 모듈의 열.응력 해석을 수행하였다. 패키지 재료에 의한 영향을 살피고자 AIN과 $A1_2O_3$절연기판을 사용한 경우를 비교하였으며, 적층구조의 규격을 변화시켜 열해석 및 열응력 해석결과를 비교하였다. 열해석 경계조건 설정에 따른 차이를 비교하기 위하여 등가열전달계수 경계조건(FHTCC)과 일정온도 경계조건(CTC)으로 나누어 해석하였다. 절연기판 면적의 증가는 열저항 감소에 거의 기여하지 못하였으나 열응력 감소에는 상당한 효과를 보였는데, 기판면적이 3배 넓어지면 열저항 감소분은 $A1_2O_3$ 절연기판 모듈에서 8.9%정도, AIN 절연기판 모듈에선 1.5% 정도 감소하는데 그쳤으나 열응력은 최고 60%의 감소를 보였다. 또한 솔더의 두께가 증가할수록 열저항은 증가하였으나, 열응력은 감소 또는 일정하게 유지함을 확인하였다. 각 모듈에서 최대응력값은 모두 절연기판과 접촉된 상, 하부 Cu pad에서 발생하였으며 모듈 패키지 가장자리 부분보다는 중앙부의 응력값이 높았다.

• 한국전기전자재료학회논문지
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• 제26권4호
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• pp.330-334
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• 2013

We developed a package of remote phosphor structure having blue LED chips and phosphors physically separated, and the characteristics were evaluated according to different classifications of phosphor coatings. Remote phosphor was produced by screen printing coating on glass substrate with phosphor content rated paste and heat treatment. After mounting Remote phosphor, which has been classified according to number of coatings, on top of blue LED chips, luminous flux, luminous efficacy, CCT and CRI were measured. The measurement results showed the most suitable characteristics of white LED package as a general light source when the content rate of phosphor in Remote phosphor was 80 wt.% with 3 layers of coatings and thickness over $12{\mu}m$.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2002년도 International Symposium
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• pp.21-30
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• 2002

According the difference of flex substrate, (reel tape), there are three kind assembly types of LCD driver IC is COG, TCP and COF, respectively. The TCP is the maturest in these types for stability of raw material supply and other specification. And TCP is the major assembly type of LCD driver IC and the huge demand from Taiwan's large TFT LCD panel house since this spring. But due to its package structure and the raw material applied in this package, there is some limitation in fine pitch application of this package type, (TCP). So, COF will be very potential in compact and portable application comparison with TCP in the future. There are three kinds assembly methods in COF, one is ACF by using the anisotropic conductive film to connect the copper lead of tape and gold bump of IC, another is eutectic bonding by using the thermo-pressure to joint the copper lead of tape and gold bump of IC, and last is NCP by using non-conductive paste to adhere the copper lead of tape and gold bump of IC. To have a global realization, this paper will briefly review the status of Taiwan's large TFT panel house, the internal driver IC design house, and the back-end assembly house in the beginning. The different material property of raw material, PI tape is also compared in the paper. The more detail of three kinds of COF assembly method will be described and compared in this paper.

• 한국재료학회지
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• 제17권2호
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• pp.91-95
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• 2007

Electromigration characteristics of Sn-3.5Ag flip chip solder bump were analyzed using flip chip packages which consisted of Si chip substrate and electroplated Cu under bump metallurgy. Electromigration test temperatures and current densities peformed were $140{\sim}175^{\circ}C\;and\;6{\sim}9{\times}10^4A/cm^2$ respectively. Mean time to failure of solder bump decreased as the temperature and current density increased. The activation energy and current density exponent were found to be 1.63 eV and 4.6, respectively. The activation energy and current density exponent have very high value because of high Joule heating. Evolution of Cu-Sn intermetallic compound was also investigated with respect to current density conditions.

• 조명전기설비학회논문지
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• 제27권9호
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• pp.1-5
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• 2013

We developed high-efficient 6W-LED package with simple structure by applying Heat Slug and silicone-reflector. LED package was manufactured in $8.5{\times}8.5mm$ sized multi-chip structure having thickness of $500{\mu}m$ achieved by bonding silicon-reflector with prepreg on top of the plate after implementing the reflector placed on copper substrate Half Etching by thickness of $200{\mu}m$. The luminous flux, luminous efficacy, correlated color temperature, color rendering index and thermal resistance of developed LED was evaluated, and it verified the application of products by applying it to 120W-LED road luminaires through simulation. The luminous efficacy of LED package reached over 130lm/W, and it is possible to be manufactured into 120W-LED road luminaires using 18 packages. In addition, the simulation results showed average of horizontal illuminance and overall illuminance uniformity that is suitable for three-lane road.