• 제목/요약/키워드: Package Level Test

검색결과 223건 처리시간 0.028초

가속열화시험을 적용한 MEMS 진공패키지의 신뢰성 분석 및 개선 (Reliability Assessment and Improvement of MEMS Vacuum Package with Accelerated Degradation Test (ADT))

  • 최민석;김운배;정병길;좌성훈;송기무
    • 한국신뢰성학회지:신뢰성응용연구
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    • 제3권2호
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    • pp.103-116
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    • 2003
  • We carry out reliability tests and investigate the failure mechanisms. of the wafer level vacuum packaged MEMS gyroscope sensor using an accelerated degradation test. The accelerated degradation test (ADT) is used to evaluate reliability (and/or life) of the MEMS vacuum package and to select the accelerated test conditions, which reduce the reliability testing time. Using the failure distribution model and stress-life model, we are able to estimate the average life time of the vacuum package, which is well agreed with the measured data. After improving several package reliability issues such as prevention of gas diffusion through package, we carry out another set of accelerated tests at the chosen acceleration level. The results show that reliability of the vacuum packaged gyroscope has been greatly improved and can survive without degradation of performance, which is the Q-factor in gyroscope sensor, during environmental stress reliability tests.

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방사성물질 운반용기의 적층시험조건에 대한 안전성 평가 (Safety Evaluation of Radioactive Material Transport Package under Stacking Test Condition)

  • 이주찬;서기석;유성연
    • 방사성폐기물학회지
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    • 제10권1호
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    • pp.37-43
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    • 2012
  • IAEA 및 국내의 방사성물질 운반 관련 규정에 따라 중 저준위 방사성폐기물 드럼 8개를 운반할 수 있는 IP-2형 운반용기를 개발하였다. IP-2형 운반용기는 낙하시험 및 적층시험을 거친 후 내용물의 유실 또는 분산과 운반용기 외부표면에서의 방사선량률이 20 % 이상 증가할 수 있는 차폐능력의 상실이 없어야 한다. 본 연구의 목적은 적층시험조건에 대한 시험방법 및 절차를 수립하고 IP-2형 운반용기의 적층조건에 대한 구조적 건전성을 평가하는데 있다. 운반용기의 원형시험모델을 이용하여 운반용기 중량의 5배 하중으로 24시간 동안 압축하는 적층조건에 대한 시험 및 전산해석을 수행하였다. 적층시험 시 운반용기의 모서리기둥에서의 변형률 및 변위를 측정하였으며, 측정된 변형률 및 변위는 해석결과와 서로 일치하였다. 컨테이너 바닥부의 처짐량은 측정이 어렵기 때문에 전산해석 방법으로 구하였다. 모서리기둥의 최대 변위와 컨테이너 바닥의 최대 처짐은 법규에서 규정하는 허용치에 비하여 낮게 나타났다. 적층시험 전 후에는 운반용기의 외형치수, 차폐체 두께, 볼트토크 등을 측정하였으며, 그 값들을 비교분석한 결과 운반용기는 내용물의 유실 및 분산, 차폐체 두께의 감소가 나타나지 않았다. 따라서 적층시험조건에서 IP-2형 운반용기의 구조적 건전성이 입증되었다.

Board Level Reliability Evaluation for Package on Package

  • 황태경
    • 한국마이크로전자및패키징학회:학술대회논문집
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    • 한국마이크로전자및패키징학회 2007년도 SMT/PCB 기술세미나
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    • pp.37-47
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    • 2007
  • Factor : Structure Metal pad & SMO size Board level TC test : - Large SMO size better Board level Drop test : - Large SMO size better Factor : Structure Substrate thickness Board level TC test : - Thick substrate better Board level Drop test : - Substrate thickness is not a significant factor for drop test Factor : Material Solder alloy Board level TC test : - Not so big differences over Pb-free solder and NiAu, OSP finish Board level Drop test : - Ni/Au+SAC105, CuOSP+LF35 are better Factor : Material Pad finish Board level TC test : - NiAu/NiAu is best Board livel Drop test : - CuOSP is best Factor : Material Underfill Board level TC test - Several underfills (reworkable) are passed TCG x500 cycles Board level Drop test : - Underfill lots have better performance than non-underfill lots Factor : Process Multiple reflow Board level TC test : - Multiple reflow is not a significant actor for TC test Board level Drop test : N/A Factor : Process Peak temp Board level TC test : - Higher peak temperature is worse than STD Board level Drop test : N/A Factor : Process Stack method Board level TC test : - No big difference between pre-stack and SMT stack Board level Drop test : - Flux dipping is better than paste dipping but failure rate is more faster

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반도체 테스트 소켓의 검사속도 및 반복 정밀도 개선형 검사장치에 관한 연구 (A Study on the Test Device for Improving Test Speed and Repeat Precision of Semiconductor Test Socket)

  • 박형근
    • 한국산학기술학회논문지
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    • 제22권1호
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    • pp.327-332
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    • 2021
  • 패키지레벨에서 반도체의 신뢰성 검사는 테스트 소켓에 반도체 칩 패키지를 탑재시킨 상태에서 테스트가 진행되며, 테스트 소켓은 기본적으로 반도체 칩 패키지의 형태에 따라서 그 모양이 결정되는 것이 일반적이다. 또한, 반도체 칩 패키지의 리드와 소켓 리드의 기계적인 접촉에 의해 테스트 장비와 연결하는 매개체의 역할을 하며, 신호전달 과정에서 신호의 손실을 최소화하여 반도체에 검사신호를 잘 전달할 수 있도록 하는 기능이 핵심이다. 본 연구에서는 이웃하고 있는 전기 전달 경로의 상호 영향성을 검사 할 수 있는 기술을 적용함으로써 수명 검사와 정밀 측정뿐만 아니라 이웃하고 있는 전기 전달 경로의 구조를 포함하여 단 한 번의 접촉을 통해 100개미만의 실리콘 테스트 소켓의 합선 테스트가 가능하도록 개발하였다. 개발된 장치의 테스트 결과 99%이상의 테스트 정밀도와 0.66이하의 동시 검사속도 특성을 나타내었다.

의료서비스의 내부마케팅 전략수립을 위한 내부고객세분화와 보상정책의 적용에 관한 연구 (The Internal Marketing Strategy for the Performance of Medical Service -A Focus on the Compensation Package for the Internal Customers-)

  • 백수경
    • 한국병원경영학회지
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    • 제6권3호
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    • pp.90-108
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    • 2001
  • This research examines the compensation package maximizing the utilities of internal customers by applying the market segmentation theory. Data were collected from four Korean hospitals in Seoul, Pusan and Kyunggi-do. The research is designed to seek the compensation package maximizing the utility of doctors and nurses by applying the market segmentation theory. The compensation package for doctors and nurses was classified into 5 attributes which are level of salary, payment method, education, promotion, reward method. The test results were as follows. First, the relative importance of each attribute in the compensation package is different. The level of salary is the most important, reward method is the next. Second, the utility of doctors increases by 8.7%, when they are segmented on the basis. of their preference for compensation attributes while that of nurses increases by 39.8%. The results of this study imply that the utility of doctors and nurses increases with differentiated compensation package for internal customer segmented by their preference.

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셀 레벨에서의 OPTICS 기반 특질 추출을 이용한 칩 품질 예측 (A Prediction of Chip Quality using OPTICS (Ordering Points to Identify the Clustering Structure)-based Feature Extraction at the Cell Level)

  • 김기현;백준걸
    • 대한산업공학회지
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    • 제40권3호
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    • pp.257-266
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    • 2014
  • The semiconductor manufacturing industry is managed by a number of parameters from the FAB which is the initial step of production to package test which is the final step of production. Various methods for prediction for the quality and yield are required to reduce the production costs caused by a complicated manufacturing process. In order to increase the accuracy of quality prediction, we have to extract the significant features from the large amount of data. In this study, we propose the method for extracting feature from the cell level data of probe test process using OPTICS which is one of the density-based clustering to improve the prediction accuracy of the quality of the assembled chips that will be placed in a package test. Two features extracted by using OPTICS are used as input variables of quality prediction model because of having position information of the cell defect. The package test progress for chips classified to the correct quality grade by performing the improved prediction method is expected to bring the effect of reducing production costs.

A Study on the/ Correlation Between Board Level Drop Test Experiment and Simulation

  • Kang, Tae-Min;Lee, Dae-Woong;Hwang, You-Kyung;Chung, Qwan-Ho;Yoo, Byun-Kwang
    • 마이크로전자및패키징학회지
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    • 제18권2호
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    • pp.35-41
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    • 2011
  • Recently, board level solder joint reliability performance of IC packages during drop impact becomes a great concern to semiconductor and electronic product manufacturers. The handheld electronic products are prone to being dropped during their useful service life because of their size and weight. The IC packages are susceptible to solder joint failures, induced by a combination of printed circuit board (PCB) bending and mechanical shock during impact. The board level drop testing is an effective method to characterize the solder joint reliability performance of miniature handheld products. In this paper, applying the JEDEC (JESD22-B111) standard present a finite element modeling of the FBGA. The simulation results revealed that maximum stress was located at the outermost solder ball in the PCB or IC package side, which consisted well with the location of crack initiation observed in the failure analysis after drop reliability tests.

솔더볼 조성에 의한 피로강도의 영향 (Effects of Fatigue Strength by Solder Ball Composition)

  • 김경수;김진영
    • 한국진공학회지
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    • 제13권3호
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    • pp.127-131
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    • 2004
  • BGA(ball grid array) package에서 솔더볼의 피로강도에 대한 솔더 조성에 대한 영향을 조사하기 위하여 패키지 신뢰성 시험을 실시하였다. 공정조성 솔더 63Sn/37Pb, 62Sn/36Pb/2Ag, 63Sn/34.4Pb/2Ag/0.5Sb 솔더를 이용하여 제조된 시편을 MRT Lv3 (moisture resistance test level) 조건에서 전처리 후 T/C(temperature cycle test) 실험을 수행하였다. 각각의 신뢰성 시험에 대하여 전단강도를 측정하였으며, 미세 조직 사진을 얻었다. 또한, SEM (scanning electron microscope)과 EDX (energy dispersive X-ray)를 이용하여 파괴 기구에 대한 분석을 실시하였다. Sn63Pb34.5Ag2Sb0.5 솔더에서 Au-Sn 성장비는 63Sn/37Pb, 62Sn/36Pb/2Ag 솔더에 비해 느리다 솔더 조성에 따른 솔더볼의 전단응력 저하에 대하여 논의하였다.

유리 기판과 패인 홈 모양의 홀을 갖는 웨이퍼를 이용한 웨이퍼 레벨 패키지 (Wafer Level Package Using Glass Cap and Wafer with Groove-Shaped Via)

  • 이주호;박해석;신제식;권종오;신광재;송인상;이상훈
    • 전기학회논문지
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    • 제56권12호
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    • pp.2217-2220
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    • 2007
  • In this paper, we propose a new wafer level package (WLP) for the RF MEMS applications. The Film Bulk Acoustic Resonator (FBAR) are fabricated and hermetically packaged in a new wafer level packaging process. With the use of Au-Sn eutectic bonding method, we bonded glass cap and FBAR device wafer which has groove-shaped via formed in the backside. The device wafer includes a electrical bonding pad and groove-shaped via for connecting to the external bonding pad on the device wafer backside and a peripheral pad placed around the perimeter of the device for bonding the glass wafer and device wafer. The glass cap prevents the device from being exposed and ensures excellent mechanical and environmental protection. The frequency characteristics show that the change of bandwidth and frequency shift before and after bonding is less than 0.5 MHz. Two packaged devices, Tx and Rx filters, are attached to a printed circuit board, wire bonded, and encapsulated in plastic to form the duplexer. We have designed and built a low-cost, high performance, duplexer based on the FBARs and presented the results of performance and reliability test.