• Journal of Power Electronics
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• v.13 no.1
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• pp.113-121
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• 2013

This paper introduces a simple core loss calculation method for output filter inductor in pulse width modulation (PWM) DC-AC inverter. Amorphous C-core (AMCC-320) is used to analyze the core loss. In order to measure core loss of the output filter inductor and validate the proposed method, a single-phase half-bridge inverter and a calorimeter are used. By changing switching frequency and modulation index (MI) of the inverter, core loss of the AMCC-320 is measured with the lab-made calorimeter and the results are compared with calculated core loss. The proposed method can be easily extended to other core loss calculation of various converters.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.12 no.5
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• pp.505-518
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• 1987

In this paper, the 2-level and 3-level types of PWM technique have been analyzed, and a multiprocessor has been designed as controller for these two types of PWM inverters. Designed multiprocessor employing a hierarchical structure of a SUPERVISORY PROCESSOR which interconnects three LOCAL PROCESSOR through a common memory technique has showed as elaborate digital control characteristic. Using this multiprocessor configuration the system could gain a great degree of freedom in change of software. Also software was simpler than a single processor configuration.

• Proceedings of the KIPE Conference
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• 2001.07a
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• pp.223-226
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• 2001

In this paper, dc link ripple currents for three-phase ac/dc/ac PWM converters are analyzed in a frequency domain. The expression of the harmonic currents is developed by using switching functions and exponential Fourier series expansion. The dc link ripple currents with regard to power factor and modulation index are investigated. In addition, the effect of the displacement angle between the switching periods of line-side converters and load-side inverters on the do link ripple current is studied. The result of the do link current analysis is helpful in specifying the dc link capacitor size and its life time estimation.

• The Transactions of the Korean Institute of Power Electronics
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• v.9 no.5
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• pp.438-447
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• 2004

A new multilevel PWM inverter using a half-bridge and full-bridge cells is proposed for the use of stand-alone photovoltaic inverters. The configuration of the proposed multilevel PWM inverter is based on a prior 11-level shaped PWM inverter. Among three full-bridge cells employed in the prior inverter, one cell is substituted by a half-bridge cell. Owing to this simple alteration, the proposed inverter has three promising merits. First it increases the number of output voltage levels resulted in high quality output voltages. Second, it reduces two power switching devices by means of employing a half-bridge cell. Third, it reduces power imposed on a transformer connected with the half-bridge unit. That is to say, most power is transferred to loads via cascaded transformers connected with low switching inverters, which are used to synthesize the fundamental output voltage levels whereas the output of a transformer linked to a high switching inverter is used to improve the final output voltage waves; thus, it is desirable in the point of the improvement of the system efficiency. By comparing to the prior 11-level PWM inverter, it assesses the performance of the proposed inverter as a stand-alone photovoltaic inverter. The validity of the proposed inverter is verified by computer-aided simulations and experimental results.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.62 no.4
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• pp.502-509
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• 2013

It presents an efficient switching pattern, which expects a reduction of switching losses in a cascaded H-bridge PWM multilevel inverter. By the proposed switching scheme, the lower H-bridge module operates at low frequency of 60[Hz] because it assigns to transfer most load power. The upper H-bridge module operates at high frequency of PWM switching to improve THD of output voltage. The proposed switching pattern applies to cascaded H-bridge multilevel inverter with PD, APOD, bipolar, and unipolar switching methods. By computer-aided simulations, we verify the validity of the proposed switching scheme. Finally, we prove that the proposed PD and APOD switching patterns are better than those of the conventional one in efficiency.

• Journal of Power Electronics
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• v.17 no.1
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• pp.106-114
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• 2017

In this paper, the Selective Harmonic Mitigation-PWM (SHM-PWM) method is used in single-phase and three-phase Cascaded H-Bridge (CHB) inverters in order to fulfill different power quality standards such as EN 50160, CIGRE WG 36-05, IEC 61000-3-6 and IEC 61000-2-12. Non-equal DC link voltages are used to increase the degrees of freedom for the proposed SHM-PWM technique. In addition, it will be shown that the obtained solutions become continuous and without sudden changes. As a result, the look-up tables can be significantly reduced. The proposed three-phase modulation method can mitigate up to the 50th harmonic from the output voltage, while each switch has just one switching in a fundamental period. In other words, the switching frequency of the power switches are limited to 50 Hz, which is the lowest switching frequency that can be achieved in the multilevel converters, when the optimal selective harmonic mitigation method is employed. In single-phase mode, the proposed method can successfully mitigate harmonics up to the 50th, where the switching frequency is 150 Hz. Finally, the validity of the proposed method is verified by simulations and experiments on a 9-level CHB inverter.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.49 no.9
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• pp.618-625
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• 2000

Recently PWM inverters are widely utilized for many industrial applications e.g. high performance motor drive and PWM techniques are newly developed for an accurate output voltage. Among them space voltage vector PWM(SVPWM) inverter has high voltage ratio and low harmonics compared to the conventional sinusoidal PWM inverter. However output voltage of PWM inverter is distorted and has error duet o the conducting voltage drop of switching devices and the dead time that is inevitable to prevent the shoot-through phenomenon. This paper investigates 3-phase SVPWM inverter which has a new compensation method against dead time and voltage drop. Proposed algorithm calculates gate pulse periods which directly compensates the dead time and nonlinear voltage drop without modification of reference voltages. Direct compensation of gate pulse periods produces exact output voltage and does not need additional circuits. The propose algorithm is verified through the simulation and experiments.

• The Transactions of the Korean Institute of Power Electronics
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• v.19 no.4
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• pp.376-382
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• 2014

This paper proposes the pulse width modulation (PWM) control strategy for low-speed operation in the three-level neutral-point-clamped (NPC) inverters based on the bootstrap gate drive circuit. As a purpose of the cost reduction, several papers have paid attention to the bootstrap circuit applied to the three-level NPC inverter. However, the bootstrap gate driver IC cannot generate the gate signal to the IGBT for low-speed operation, because the bootstrap capacitor voltage decreases under the threshold level. For low-speed operation, the dipolar and partial-dipolar modulations can be the effective solution. However, these modulations have drawbacks in terms of the switching loss and THD. Therefore, this paper proposes the PWM control strategy to operate the inverter at low-speed and to minimize the switching loss and harmonics. The experimental results are presented to verify the validity on the proposed method.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.20 no.3
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• pp.36-44
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• 2006

In general, the generated harmonics and noise of the PWM inverter are affected by PWM switching method, switching frequency, dv/dt and di/dt. Since multilevel inverters are often applied to the high power system, and operates with low switching frequency, theyproduce large size of harmonic contents and noise. Thus it is necessary to install output filters in the multilevel inverter. In this paper a filter design approach for the harmonic and noise reduction the three phase induction motor driving system using H-bridge 7-level inverter system is presented. The passive filter that has low cost and simple structure and can effectively reduce harmonics and noise, is designed and applied to the three phase induction motor drive having multilevel inverter system. The designed system is implemented and verified by simulation and experiments.

• Proceedings of the KIEE Conference
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• 2003.10b
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• pp.216-219
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• 2003

The resonant inverter is widely used for induction heating, electronic ballast and supersonic motor driving circuit. In the meantime, control techniques of PWM, PFM etc.. are mainly applied to control the output power of the resonant inverter. But, in the case of using the half bridge resonant inverter, it is difficult to control the output power by PWM, because its main circuit does not provide the load free-wheeling mode. Therefore, PAM or PFM was usually applied to control output power of half bridge resonant inverter. However, PAM needs a variable DC voltage source, which makes the system structure more complex. On the other hand, in case of PFM, efficiency is declined by operation with poor power factor. This paper Proposed the novel half bridge resonant inverter which can provide the load free-wheeling mode. Also its analysis results for PWM operation with unity fundamental power factor are Presented and compared with other resonant inverters using PWM and PFM.