• Title/Summary/Keyword: PVP dielectric

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High-Performance Amorphous Indium-Gallium Zinc Oxide Thin-Film Transistors with Inorganic/Organic Double Layer Gate Dielectric

  • Lee, Tae-Ho;Kim, Jin-U;No, Yong-Han
    • Proceedings of the Korean Vacuum Society Conference
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    • 2013.02a
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    • pp.465-465
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    • 2013
  • Inorganic 물질인 SiO2 dielectric 위에 organic dielectric PVP (4-vinyphenol)를 spin coating으로 올려, inorganic/organic dielectric 형태의 double layer구조로 High-performance amorphous indiumgallium zinc oxide thin-film transistors (IGZO TFT)를 제작하여 보았다. SiO2 dielectric을 buffer layer로 80 nm, PVP는 10Wt% 400 nm로 구성하였으며, 200 nm single SiO2 dielectric과 동일한 수준의 leakage current 특성을 MIM Capacitor 구조를 통해서 확인할 수 있었다. 이 소자의 장점은 용액공정의 도입으로 공정 시간의 단축 및 원가 절감을 이룰 수 있으며, dielectric과 channel 사이의 균일한 interface의 형성으로 interface trap 개선 및 Yield 향상의 장점을 갖는다. 우리는 실험을 통해서 SiO2 buffer layer가 수직 electric field에 의한 leakage current을 제어하고, PVP dielectric은 interface를 개선하는 것을 확인하였다. Vth의 negative shift 및 slope의 향상으로 구동전압이 줄어들고, 균일한 I-V Curve 형성을 통해서 Process Yield의 향상을 확인하였다.

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Improvement of Electrical and Mechanical Characteristics of Organic Thin Film Transistor with Organic/Inorganic Laminated Gate Dielectric (유연성 유기 박막트랜지스터 적용을 위한 다층 게이트 절연막의 전기적 및 기계적 특성 향상 연구)

  • Noh, H.Y.;Seol, Y.G.;Kim, S.I.;Lee, N.E.
    • Journal of the Korean institute of surface engineering
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    • v.41 no.1
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    • pp.1-5
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    • 2008
  • In this work, improvement of mechanical and electrical properties of gate dielectric layer for flexible organic thin film transistor (OTFT) devices was investigated. In order to increase the mechanical flexibility of PVP (poly(4-vinyl phenol) organic gate dielectric, a very thin inorganic $HfO_2$ layers with the thickness of $5{\sim}20nm$ was inserted in between the spin-coated PVP layers. Insertion of the inorganic $HfO_2$ in the laminated organic/inorganic structure of PVP/$HfO_2$/PVP layer led to a dramatic reduction in the leakage current compared to the pure PVP layer. Under repetitive cyclic bending, the leakage current density of the laminated PVP/$HfO_2$/PVP layer with the thickness of 20-nm $HfO_2$ layer was not changed, while that of the single PVP layer was increased significantly. Mechanical flexibility tests of the OTFT devices by cyclic bending with 5 mm bending radius indicated that the leakage current of the laminated PVP/$HfO_2$(20 nm)/PVP gate dielectric in the device structure was also much smaller than that of the single PVP layer.

Verification of Bonding Force between PVP Dielectric Layer and PDMS for Application of Flexible Capacitive-type Touch Sensor with Large Dynamic Range (넓은 다이내믹 레인지의 유연 촉각센서 적용을 위한 PVP 유전층과 PDMS 접착력 검증)

  • Won, Dong-Joon;Huh, Myoung;Kim, Joonwon
    • The Journal of Korea Robotics Society
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    • v.11 no.3
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    • pp.140-145
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    • 2016
  • In this paper, we fabricate arrayed-type flexible capacitive touch sensor using liquid metal (LM) droplets (4 mm spatial resolution). Poly-4-vinylphenol (PVP) layer is used as a dielectric layer on the electrode patterned Polyethylene naphthalate (PEN) film. Bonding tests between hydroxyl group (-OH) on the PVP film and polydimethylsiloxane (PDMS) are conducted in a various $O_2$ plasma treatment conditions. Through the tests, we can confirm that non-$O_2$ plasma treated PVP layer and $O_2$ plasma treated PDMS can make a chemical bond. To measure dynamic range of the device, one-cell experiments are conducted and we confirmed that the fabricated device has a large dynamic range (~60 pF).

Printing of Polymer Dielectric via Optimal Blade Coating for Large-scale Low-Leakage Capacitors (대면적 저누설 커패시터를 위한 최적화 블레이드 코팅 기반 고분자 유전체 프린팅)

  • Seo, Kyeong-Ho;Bae, Jin-Hyuk
    • Journal of Sensor Science and Technology
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    • v.30 no.1
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    • pp.51-55
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    • 2021
  • We demonstrated a polymer dielectric with low leakage characteristics through an optimal blade coating method for low-cost and large-scale fabrication of metal-insulator-metal (MIM) capacitors. Cross-linked poly(4-vinylphenol) (C-PVP), which is a typically used polymer dielectric, was coated on a 10 × 10 cm indium-tin-oxide (ITO) deposited glass substrate by changing the deposition temperature (TD) and coating velocity (VC) in the blade coating. During the blade coating, the thickness of the thin c-PVP varied depending on TD and VC owing to the 'Landau-Levich (LL) regime'. The c-PVP-dielectric-based MIM capacitor fabricated in this study showed the lowest leakage current characteristics (10-6 A/㎠ at 1.2 MV/㎠, annealing at 200 ℃) and uniform electrical characteristics when TD was 30 ℃ and VC was 5 mm/s. In addition, at TD = 30 ℃, stable leakage characteristics were confirmed when a different electric field was applied. These results are expected to positively contribute to applications with next-generation electronic devices.

Interface Treatment Effect of High Performance Flexible Organic Thin Film Transistor (OTFT) Using PVP Gate Dielectric in Low Temperature (저온 공정 PVP게이트 절연체를 이용한 고성능 플렉서블 유기박막 트랜지스터의 계면처리 효과)

  • Yun, Ho-Jin;Baek, Kyu-Ha;Shin, Hong-Sik;Lee, Ga-Won;Lee, Hi-Deok;Do, Lee-Mi
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.24 no.1
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    • pp.12-16
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    • 2011
  • In this study, we fabricated the flexible pentacene TFTs with the polymer gate dielectric and contact printing method by using the silver nano particle ink as a source/drain material on plastic substrate. In this experiment, to lower the cross-linking temperature of the PVP gate dielectric, UV-Ozone treatment has been used and the process temperature is lowered to $90^{\circ}C$ and the surface is optimized by various treatment to improve device characteristics. We tried various surface treatments; $O_2$ Plasma, hexamethyl-disilazane (HMDS) and octadecyltrichlorosilane (OTS) treatment methods of gate dielectric/semiconductor interface, which reduces trap states such as -OH group and grain boundary in order to improve the OTFTs properties. The optimized OTFT shows the device performance with field effect mobility, on/off current ratio, and the sub-threshold slope were extracted as $0.63cm^2 V^{-1}s^{-1}$, $1.7{\times}10^{-6}$, and of 0.75 V/decade, respectively.

The thickness effect on surface and electrical properties of PVP layer as insulator layer of OTFTs (OTFT 소자의 절연층으로써 두께에 따른 PVP 층의 표면 및 전기적 특성)

  • Seo, Choong-Seok;Park, Yong-Seob;Park, Jae-Wook;Kim, Hyung-Jin;Yun, Deok-Yong;Hong, Byung-You
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2008.11a
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    • pp.245-245
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    • 2008
  • In this work, we describe the characterization of PVP films synthesized by spin-coater method and fabricate OTFTs of a bottom gate structure using pentacene as the active layer and polyvinylphenol (PVP) as the gate dielectric on Au gate electrode. We investigated the surface and electrical properties of PVP layer using an AFM method and MIM structure, and estimated the device properties of OTFTs including $I_D-V_D$, $I_D-V_G$, threshold voltage $V_T$, on/off ratio, and field effect mobility.

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Organic Thin Film Transistors with Cross-linked PVP Gate Dielectrics by Using Photo-initiator and PMF

  • Yun, Ho-Jin;Baek, Kyu-Ha;Park, Kun-Sik;Shin, Hong-Sik;Ham, Yong-Hyun;Lee, Ga-Won;Lee, Ki-Jun;Wang, Jin-Suk;Do, Lee-Mi
    • 한국정보디스플레이학회:학술대회논문집
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    • 2009.10a
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    • pp.312-314
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    • 2009
  • We have fabricated pentacene based organic thin film transistors (OTFTs) with formulated poly[4-vinylphenol] (PVP) gate dielectrics. The gate dielectrics is composed of PVP, poly[melamine-coformaldehyde] (PMF) and photo-initiator [1-phenyl-2-hydroxy-2-methylpropane-1-one, Darocur1173]. By adding small amount (1 %) of photo-initiator, the cross-linking temperature is lowered to $115^{\circ}C$, which is lower than general thermal curing reaction temperature of cross-linked PVP (> $180^{\circ}C$). The hysteresis and the leakage current of the OTFTs are also decreased by adding the PMF and the photoinitiator in PVP gate dielectrics.

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A Study on the Electrical Characteristics of Organic Thin Film Transistor, OTFT With Plasma-Treated Gate Insulators (Plasma 처리한 유기 절연층을 갖는 유기 박막 트랜지스터의 전기적 특성 연구)

  • 김연주;박재훈;강성인;최종선
    • Journal of the Korean Vacuum Society
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    • v.13 no.3
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    • pp.99-102
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    • 2004
  • In this work the electrical characteristics of organic thin film transistors with the surface-treated organic gate insulator have been studied. For the surface treatment of gate dielectric, Ar plasma was used. Pentacene and PVP were used as active and dielectric layers respectively. Pentacene was thermally evaporated in vacuum at a pressure of about $10^{-6}$ Torr and at a deposition rate of 0.5 $\AA$/sec. PVP was spin coated and cured at $100^{\circ}C$. before pentacene deposition. organic thin film transistors with surface-treated gate insulators have provided improved operation characteristics.

Characteristics of Pentacene Thin Film Transistors with Stacked Organic Dielectrics for Gate Insulator

  • Kang, Chang-Heon;Lee, Jong-Hyuk;Choi, Jong-Sun
    • 한국정보디스플레이학회:학술대회논문집
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    • 2002.08a
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    • pp.184-187
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    • 2002
  • In this work, the electrical characteristics of organic thin film transistors with the stacked organic gate insulators have been studied. PVP(Polyvinylphenol) and polystyrene were used as gate insulating materials. Both the high dielectric constant of PVP and better insulating capability of polystyrene were compensatorily adopted in two different stacking orders of PVP-polystyrene and polystyrene-PVP. The output characteristics of the device with the stacked gate insulator showed substantial improvement compared with those of the devices with either PVP or polystyrene gate insulator: Furthermore, these stacked organic gate insulators can differently affect the TFT characteristics with the stacking orders. The electrical properties of TFTs with organic gate insulators stacked in different orders are discussed.

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Characteristics of Pentacene Organic Thin-Film Transistors with $PVP-TiO_2$ as a Gate Insulator

  • Park, Jae-Hoon;Kang, Sung-In;Jang, Seon-Pil;Kim, Hyun-Suck;Choi, Hyoung-Jin;Choi, Jong-Sun
    • 한국정보디스플레이학회:학술대회논문집
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    • 2005.07b
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    • pp.1301-1305
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    • 2005
  • The performance of OTFT with $PVP-TiO_2$ composite, as a gate insulator, is reported, including the effect of surfactant for synthesizing the composite material. According to our investigation results, it was one of critical issues to prevent the aggregation of $PVP-TiO_2$ particles during the synthesis process. From this point of view, $PVP-TiO_2$ particles were treated using Tween80, as a surfactant, and we could reduce the aggregated $PVP-TiO_2$ clusters. As a result, the OTFT with the composite insulator showed the threshold voltage of about -8.3 V and the subthreshold slope of about 1.5 V/decade, which are the optimized properties compared to those of OTFTs with bare PVP, in this study. It is thought that these characteristic improvements are originated from the increase in the dielectric constant of the PVP-based insulator by compositing with high-k particles.

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