• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.38 no.3
• /
• pp.205-210
• /
• 2001

In this paper, a novel compound mode logic based on the advantage of both CMOS logic and pass-transistor logic(PTL) is proposed. From the experimental results, the power-delay products of the compound mode logic is about 22% lower than that of the conventional CMOS logic, when we design a full adder. With the proposed logic, a high performance 32$\times$32-bit multiplier has been fabricated with 0.6um CMOS technology. It is composed of an improved sign select Booth encoder, an efficient data compressor based on the compound mode logic, and a 64-bit conditional sum adder with separated carry generation block. The Proposed 32$\times$32-bit multiplier is composed of 28,732 transistors with an active area of 1.59$\times$1.68 mm2 except for the testing circuits. From the measured results, the multiplication time of the 32$\times$32-bit multiplier is 9.8㎱ at a 3.3V power supply, and it consumes about 186㎽ at 100MHz.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.37 no.6B
• /
• pp.433-442
• /
• 2012

We have proposed a solution to multicast services and an advanced quality of service (QoS) mechanism on a packet transport system (PTS) based on PBB-TE. The point-to-multipoint (PtMP) connection in the PBB-TE system have been realized by grouping point-to-point (PtP) PTL trunks and mapping a BSI onto the PtP PTL trunks using a multicast backbone destination address. To provide end-to-end QoS of the PtMP services, the hierarchical QoS scheme for backbone service instances and connection-oriented paths has been implemented in the PTS. For providing different capabilities for service selection and priority selection, the PTS offers to customers three basic types of the port-based, C-tagged, and S-tagged service interface defined by the IEEE 802.1ah. To offer to customers different capabilities of the layer 3 applications and services, moreover, an IP-flow service interface have been added. In order to evaluate traffic performance for PtMP services in the PTS, the PtMP throughputs for the link capacity of 1 Gbps at the four service interfaces were measured in the leaves of the ingress edge node, the transit node, and the egress edge node. The throughputs were about 96 % because the B-MAC overhead of 22 bytes occupies 4% of the 512-byte packet. The QoS performance is ability to guarantee an application or a user a required bandwidth, and could be evaluated by the accuracy of policing or shaping. The accuracy of the policing scheme and the accuracy of the shaping scheme were 99% and 99.3% respectively.

• Korean Journal of Cleft Lip And Palate
• /
• v.11 no.2
• /
• pp.49-58
• /
• 2008

The development of fetal surgery has led to promising options for many congenital malformations, such as congenital diaphragmatic hernia (CDH), obstructive uropathy, twin-to-twin transfusion syndrome (TTTS), and sacrococcygeal teratoma. However, preterm labor (PTL) and premature rupture of membranes continue to be uniquitous risks for both mother and fetus. To reduce maternal morbidity and the risk of prematurity, minimal access techniques were developed and are increasingly employed recently. Lift-threatening diseases as well as severely disabling but not life-threatening conditions are potentially amenable to treatment. Recently, improvement of video-endoscopic technology has boosted the development of operative techniques for feto-endoscopic surgery, which has been demonstrated to be less invasive than the open approach. Fetal surgery for repair of cleft lip and palate, a congenital anomaly which is not life threatening, is inappropriate until such time that the benefits are shown to outweigh the risks of both the procedure itself and preterm delivery. Further animal studies will be needed before intrauterine surgery for humans should be considered. For the better understanding of recent techniques and complications associated with fetal intervention of congenital facial defect patients, we reviewed recent related articles about the current knowledge and new perspectives of experimental fetal fetal surgery in the cleft lip and palate defects.

• Membrane Journal
• /
• v.27 no.6
• /
• pp.477-486
• /
• 2017

Hydrogen is one of energy storage systems, which could be transfer from electric energy to chemical energy or from chemical energy to electric energy, and is as an energy carrier. Water electrolysis is being investigating as one of the hydrogen production methods. Recently, water electrolysis receive attention for the element technology in PTG (power to gas) and PTL (power to liquid) system. In this paper, it was explained the principle and type for the water electrolysis, and recent research review for the alkaline water electrolysis.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.38 no.3
• /
• pp.51-51
• /
• 2001

본 논문에서는 CMOS 로직과 pass-transistor logic(PTL)의 장점만을 가진 새로운 복합모드로직(Compound Mode Logic)을 제안하였다. 제안된 로직은 VLSI설계에서 중요하게 부각되고 있는 저전력, 고속 동작이 가능하며 실제로 전가산기를 설계하여 측정 한 결과 복합모드 로직의 power-delay 곱은 일반적인 CMOS로직에 비해 약 22% 개선되었다 제안한 복합모드 로직을 이용하여 고성능 32×32-bit 곱셈기를 설계 제작하였다. 본 논문의 곱셈기는 개선된 사인선택(Sign Select) Booth 인코더, 4-2 및 9-2 압축기로 구성된 데이터 압축 블록, 그리고 carry 생성 블록을 분리한 64-bit 조건 합 가산기로 구성되어 있다. 0.6um 1-poly 3-metal CMOS 공정을 이용하여 제작된 32×32-bit 곱셈기는 28,732개의 트랜지스터와 1.59×l.68 ㎜2의 면적을 가졌다. 측정 결과 32×32-bit 곱셈기의 곱셈시간은 9.8㎱ 이었으며, 3.3V 전원 전압에서 186㎽의 전력 소모를 하였다.

• Management Science and Financial Engineering
• /
• v.17 no.2
• /
• pp.23-37
• /
• 2011

In this paper, we address a layout design problem for determining an optimal 4-class-based dedicated linear storage layout in a class of unit load storage systems. Assuming that space requirement for a class is the sum of the maximum inventory levels of products assigned to the class, and that one-way travel time is a linear function of storage index, we formulate a 4-class-based dedicated linear storage problem PTL[4] and provide an exact splitting algorithm with $O(n{\lceil}logn{\rceil})$. Our algorithms could be applied to more than a 4-class-based dedicated storage layout problem with slight modification in order to reduce computational execution time.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.37 no.4
• /
• pp.60-70
• /
• 2000

An 8$\times$8+20-bit MAC is designed with low power design methodologies at each of the system design levels. At algorithm level, a new method for multipl $y_tract operation is proposed, and it saves the transistor counts over conventional methods in hardware realization. A new Booth selector circuit using NMOS pass-transistor logic is also proposed at circuit level. It is superior to other circuits designed by CMOS in power-delay-product. And at architecture level, we adopted an ELM adder that is known to be the most efficient in power consumption, operating frequency, area and design regularity as the final adder. For registers, dynamic CMOS single-edge triggered flip-flops are used because they need less transistors per bit. To increase the operating frequency 2-stage pipeline architecture is adopted, and fast 4：2 compressors are applied in Wallace tree block. As a simulation result, the designed MAC in 0.6${\mu}{\textrm}{m}$ 1-poly 3-metal CMOS process is operated at 200MHz, 3.3V and consumed 35㎽ of power in multiply operation, and operated at 100MHz consuming 29㎽ in MAC operations, respectively.ly.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.17 no.2
• /
• pp.302-317
• /
• 2017

This paper proposes a new full adder design based on pass-transistor logic that offers ultra-low power dissipation and superior variability together with low transistor count. The pass-transistor logic allows device count reduction through direct logic realization, and thus leads to reduction in the node capacitances as well as short-circuit currents due to the absence of supply rails. Optimum transistor sizing alleviates the adverse effects of process variations on performance metrics. The design is subjected to a comparative analysis against existing designs based on Monte Carlo simulations in a SPICE environment, using the 22-nm CMOS Predictive Technology Model (PTM). The proposed ULP adder offers 38% improvement in power in comparison to the best performing conventional designs. The trade-off in delay to achieve this power saving is estimated through the power-delay product (PDP), which is found to be competitive to conventional values. It also offers upto 79% improvement in variability in comparison to conventional designs, and provides suitable scalability in supply voltage to meet future demands of energy-efficiency in portable applications.

• YAKHAK HOEJI
• /
• v.43 no.2
• /
• pp.160-168
• /
• 1999

The purpose of this study was to determine pharmacokinetic parameters of vancomycin using peak and trough plasma level (PTL) and Bayesian analysis in 20 Korean normal volunteers, 16 gastric cancer and 12 lymphoma patients and also using the compartment model dependent (nonlinear least squares regression: NLSR) and compartment model independent (Lagrange) analysis in 10 ovarian cancer patients. Nonparametric expected maximum (NPEM) algorithm for calculation of the population pharmacokinetic parameters was used, and these parameters were applied for clinical pharmacokinetic parameters by Bayesian analysis. Vancomycin was administered as dose of 1.0 g every 12 hrs for 3 days by IV infusion over 60 minutes in normal volunteers, gastric cancer and lymphoma patients. Population pharmacokinetic parameters, K and Vd in gastric cancer and lymphoma patients using NPEM algorithm were $0.158{\pm}0.014{\;}hr^{-1},{\;}0.630{\pm}0.043{\;}L/kg{\;}and{\;}0.131{\pm}0.0261{\;}hr^{-1},{\;}0.631{\pm}0.089{\;}L/kg$ respectively. The K and Vd in gastric cancer and lymphoma patients using Bayesian analysis were $0.151{\pm}0.027,{\;}0.126{\pm}0.056{\;}hr^{-1}{\;}and{\;}0.62{\pm}0.105,{\;}0.63{\pm}0.095{\;}L/kg$. The K and Vd in ovarian cancer patient using the NLSR and Lagrange analysis were $0.109{\pm}0.008,{\;}0.126{\pm}0.012{\;}hr^{-1}{\;}and{\;} 0.76{\pm}0.08,{\;}0.69{\pm}0.19{\;}L/kg$, respectively. It is necessary for effective dosage regimen of vancomycin in cancer patients to use these population parameters.

• Proceedings of the KIEE Conference
• /
• 2007.07a
• /
• pp.1468-1469
• /
• 2007

포항가속기 연구소에서는 RIS 프로젝트 사업과제의 일환인 L-band 산업용 전자빔 가속기의 제작 및 기술개발 연구를 철원의 물리기술연고소 주관으로 수행하고 있다. L-band 산업용 전자빔 가속기는 전자빔에 의한 고분자개질 공정, 농수산물의 멸균 및 의료기기의 멸균 등에 적용이 가능하다. 포항가속기연구소에서는 10 MeV급 산업용 전자빔 조사장치에 적용되는 RF증폭기용 펄스 전원장치인 모듈레이터를 설계, 제작을 하였다. 펄스 전원장치인 이 모듈레이터 시스템은 평균 출력 60 kW, 펄스폭 7 us, 펄스반복율 300 Hz의 L-band 상업용 RF 증폭기 전원장치이며, RF 증폭기로 사용되는 클라이스트론은 Thales 사의 TV2022D를 사용하였다. 본 논문에서는 펄스 전원장치인 모듈레이터의 운전과 인터록을 위한 제어장치의 개발과 제작에 대하여 논하고자 한다.