• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.3
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• pp.66-74
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• 1999

InAlGaAs/InGaAs HBTs with the various emitter junction gradings(xf=0.0-1.0) and the modified collector structures (collector- I;n-p-n, collector-II;i-p-n) are simulated and analyzed by HMC (Hybrid Monte Carlo) method in order to find an optimum structure for the shortest transit time. A minimum base transit time($ au$b) of 0.21ps was obtainsed for HBT with the grading layer, which is parabolically graded from $x_f$=1.0 and xf=0.5 at the emitter-base interface. The minimum collector transit time($\tau$c) of 0.31ps was found when the collector was modified by inserting p-p-n layers, because p layer makes it possible to relax the electric field in the i-type collector layer, confining the electrons in the $\Gamma$-valley during transporting across the collector. Thus InAlGaAs/InGaAs HBT in combination with the emitter grading($x_f$=0.5) and the modified collector-III showed the transit times of 0.87 psec and the cut-off frequency (f$\tau$) of 183 GHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.7
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• pp.704-709
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• 2007

In this paper, a CPW band-pass filter with a rejection band is proposed for UWB(Ultra-Wideband) communication systems. The proposed filter has a band-pass characteristic of wide-band by inserting only a slot in $50{\Omega}$ transmission line. To obtain the band-rejection function at WLAN frequency band($5.15{\sim}5.725GHz$), the designed filter is combined with folded slot resonators on the ground plane of the CPW structure. The fabricated CPW band-pass filter shows a compact size of $15.35{\times}13.60mm$, a wide passband of 2.8 GHz to 9.8 GHz and the narrow stop-band of 5.15 GHz to 5.71 GHz for 3-dB bandwidth. Also, the measured group delay is less than 400 psec throughout the operation frequency band except the rejection band.

• Journal of Advanced Navigation Technology
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• v.10 no.1
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• pp.13-19
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• 2006

In this paper, Gaussian impulse generator for DS-UWB was proposed and fabricated so that the frequency band allocated to WLAN, around 5 GHz, was suppressed in accordance with the regulation of radiation spectrum limitation defined by FCC. In order to transform an unipolar rectangular signal to a Gaussian impulse, the proposed impulse generator consists of two stage impulse generation parts; the first stage using dual SRD and the second stage using gain switching of semiconductor laser diode. The result shows a gaussian impulse as narrow as 180 psec in width. In addition, high order derivative Gaussian filter with a structure of 4 stage ring resonators was designed and fabricated so that DS-UWB impulse generator could reduce the frequency spectrum of WLAN by 25 dB compared to the spectral power of th adjacent UWB band.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.6 s.336
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• pp.61-66
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• 2005

In this paper, we implemented a impulse generator, the one of the part in UWB(Ultra Wide Band) system using step recovery diode(SRD) and gain-switced semiconductor laser. The impulse generator was consisted of four stages; The first stage used SRD to generate the first impulse for gain switching. The second stage controled current for the suitable gain switching condition. The third was the second impulse generator to generate gaussian pulse. For gain switching, the first impulse was applied to semiconductor laser. In the last stage the gain switched impulse was converted into mono-gaussian pulse. The measured mono-gaussian pulse was 360 psec pulse-width and $-70mV \~ +50mV$ amplitude in time domain. In frequency domain its magnitude and bandwidth was, respectively, -41dBm and 3.6GHz. Accordingly, the impulse generator that we suggested was suitable for UWB systems.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.4
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• pp.1-8
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• 2004

A novol clock distribution scheme is proposed for high-speed and low-power digital system to minimize clock skew and reduce dynamic power consumption. This scheme has ideal zero-skew characteristic by using folded clock lines (FCL) and phase blending circuit. For analyzing suitable line structures to FCLs, microstrip line and coplanar line are placed with folded clock lines. Simulation results show that the maximum clock-skew between two receivers located 10mm apart is less than lops at 1㎓ and the maximum clock-skew between two receivers located 20mm apart is less than 60ps at 1㎓. Also the results show that the minimum skews of clock signals regardless of process, voltage, and temperature variation are invariant.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.2
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• pp.94-101
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• 1989

Transport properties of 2DEG at AlGaAs/GaAs interface such as average electron energy, flight distance, each valley occupancy ratio, average electron velocity for various fields are investigated by MONTE-CARLO method. As the electric field increases, more electrons transit drastically from (000) valley to (000) upper valley. This phenomenon shows the nonstationary effect such as velocity overshoot. The duration of the transient decreases from about 1.4 psec for electric field E = 7KV/cm to about 0.7 psec for 12KV/cm. The average electron velocity during transient transport in 2DEG is about 8 times the steady-state velocity for E = 12KV/cm at room temperature. In comparison with bulk GaAs the peak velocity in the 2DEG is higher than that in even pure bulk GaAs at electric field E = 7 KV/cm. On the basis of the fact that the electrons in the 2DEG have larger peak velocity and shorter transient time of velocity than those in the bulk GaAs, it is suggested that the device with 2DEG may obtain higher mobility than that with bulk GaAs.

• Proceedings of the Korean Information Science Society Conference
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• 2002.10e
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• pp.211-213
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• 2002

가상사설망이 중요한 정보를 원격에 전송한다는 개념만으로 여겨질 때에는 암호화강도에 주목했었다. 그러나 가상사설망 시장이 활성화되면서 보다 많은 트래픽을 효율적으로 처리하기 위하여, 가상사설망 고성능화에 대한 요구가 증대되고 있다. 본 논문에서는 가상사설망에서 성능 측정 시 필요한 항목들을 제시하고 설치한 네트워크 성능에 얼마만큼의 영향을 미치는지에 대해 살펴본다. 이를 위해 네트웍 환경을 IPsec 프로토콜을 사용하는FreeS／WAN 패키지를 활용하여 구성해보고, 자신의 독자적인 프로토콜인 CIPE 프로토콜을 사용하는 cIPe 패키지를 사용하여 다양한 성능지표들을 반영한 성능 측정을 실시하였다. Psec 표준을 준수하여 구현된 FreeS／WAN은 적용하는 방법에 따라 네트워크 성능 차가 상대적으로 크고 cIPe 방법은 암호화 적용 전에 비해서 그다지 큰 차이를 보이지는 않는다. 본 결과들을 고려할 경우, 가상사설망의 성능과 보안을 적절히 유지하는 범위에서 정책과 시스템 사양을 고려하여 가상사설망을 도입하여야 할 것이다.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.137-140
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• 2001

This paper shows an asynchronous comparator circuit for 1.2Gbps signal receiver that converts 1.2Gbps data rate input signals with less than 100㎷ swing to on-chip CMOS compatible voltage levels in a 0.35${\mu}{\textrm}{m}$ CMOS process. Folded-cascode nMOS input stage with source-coupled pMOS input stage cover rail-to-rail input common-mode range. Drastic gain-bandwidth increment due to gain-boosting stage with positive-feedback latch as well as wide input common-mode range make designed circuit be suitable for a fully differential signal receiver. HSPICE simulation results show that worst-case sensitivity is less than 20㎷ and maximum propagation delay is 640-psec. And also we verified 3.97㎽ power consumption with 150㎷ differential swing amplitude at 1.2Gbps.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.5 s.96
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• pp.482-487
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• 2005

In this paper, we propose the control method of output impedance of each cascode unit cell of distributed amplifier by connecting varactors in the gate-terminal of common gate. Compared to common source unit cell, cascode unit cell has many advantages such as high gain and high output impedance as well as negative resistance loading. But if the transistor model which is used in design is inaccurate and process parameter is changed, oscillation sometimes can occur at band edge in which the gain start to drop. Therefore, we need control circuit which can prevent oscillation, although the circuit has already fabricated, and varactor connected to gate-terminal of common gate of cascode gain cell can play that part. Measured result of fabricated distributed amplifier shows the capability of contol of gain characteristic by adjusting of value of varactors, this can guarantee the stability of the circuit. The gain is $8.92\pm0.82dB$ over 49 GHz, the group delay is $\pm9.3 psec$ over 41 GHz. All transistor which has $0.15{\mu}m$ gate length is GaAs based p-HEMT, and distributed amplifier is put together with 4 stages.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.23-30
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• 2005

This paper describes a DLL(delay locked loop)-based multi-clock generator having the lower active stand-by power as well as a fast relocking after re-activating the DLL. for low power and high speed VLSI chip. It enables a frequency multiplication using frequency multiplier scheme and produces output clocks with 50:50 duty-ratio regardless of the duty-ratio of system clock. Also, digital control scheme using DAC enables a fast relocking operation after exiting a standby-mode of the clock system which was obtained by storing analog locking information as digital codes in a register block. Also, for a clock multiplication, it has a feed-forward duty correction scheme using multiphase and phase mixing corrects a duty-error of system clock without requiring additional time. In this paper, the proposed DLL-based multi-clock generator can provides a synchronous clock to an external clock for I/O data communications and multiple clocks of slow and high speed operations for various IPs. The proposed DLL-based multi-clock generator was designed by the area of $1796{\mu}m\times654{\mu}m$ using $0.35-{\mu}m$ CMOS process and has $75MHz\~550MHz$ lock-range and maximum multiplication frequency of 800 MHz below 20psec static skew at 2.3v supply voltage.