• 제목/요약/키워드: PS: Power Supply

검색결과 68건 처리시간 0.024초

A 32nm and 0.9V CMOS Phase-Locked Loop with Leakage Current and Power Supply Noise Compensation

  • Kim, Kyung-Ki;Kim, Yong-Bin
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제7권1호
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    • pp.11-19
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    • 2007
  • This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using a nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit which becomes more serious problem due to the thin gate oxide and small threshold voltage in nanometer CMOS technology and the PSN compensation circuit decreases the effect of power supply variation on the output frequency of VCO. The PLL design is based on a 32nm predictive CMOS technology and uses a 0.9V power supply voltage. The simulation results show that the proposed PLL achieves a 88% jitter reduction at 440MHz output frequency compared to the PLL without leakage compensator and its output frequency drift is little to 20% power supply voltage variations. The PLL has an output frequency range of $40M{\sim}725MHz$ with a multiplication range of 11023, and the RMS and peak-to-peak jitter are 5ps and 42.7ps, respectively.

스너버 커패시터를 이용한 CCPS용 FB-PS-ZVS DC-DC 컨버터의 IGBT Turn-off 손실에 관한 연구

  • 이용덕;김상현;김태형;인동석;김주훈
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 2010년도 하계학술대회 논문집
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    • pp.572-573
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    • 2010
  • 본 논문은 30kW급 CCPS(Capacitor Charging Power Supply)용 FB(Full Bridge)-PS(Phase Shift)- Zero Voltage Switching(ZVS) DC/DC Converter의 스위칭 손실저감을 위한 스너버 커패시터의 설계에 대해 논하였다. FB-PS-ZVS DC-DC 컨버터의 하드스위칭 손실과 스너버 커패시터에 의한 스위칭 손실 저감 효과를 비교했다. 첨두 전류를 이용하여 스너버 커패시터를 설계하였으며, 부하 실험을 통해 설계의 타당성을 실험적으로 검증했다.

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전 디지털제어 전원장치 (Fully Digital Controlled Power Supply for PLS)

  • 하기만;김윤식;이성근
    • 한국마린엔지니어링학회:학술대회논문집
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    • 한국마린엔지니어링학회 2005년도 전기학술대회논문집
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    • pp.1011-1015
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    • 2005
  • Fully digital controlled 20-bit magnet power supplies have been developed and successfully tested for closed orbit correction of PLS(Pohang Light Source). The new digital power supply has used fiber optics for 25kHz switching of IGBT drivers, and implemented DSP, ADC, Interlock, DCCT cards in a compact 3U-sized 19" chassis. Input/Output low-pass filters suppress harmonics of 60Hz line frequency and switching frequency noise effectively. Overall performance of the power supplies have been demonstrated as +/- 2ppm short-term stability(<1 min), and +/- 10ppm long-term stability(<36 hours). All the existing 12-bit 70 power supplies for vertical correction magnets will be replaced with new digital power supplies during 2005 summer shutdown period. In this paper, we will describe the hardware structure and control method of the digital power supply and the experimental results will be shown.

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디젤 자동차의 에어컨 사용시 흡기계통 개선에 따른 출력 및 매연 특성에 관한 연구 (A Study on the Power and Smoke Characteristics for the Intake System Improvement using Air Conditioning System in a Diesel Vehicle)

  • 윤영춘;권기린;편훈
    • 동력기계공학회지
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    • 제15권6호
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    • pp.11-15
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    • 2011
  • This study investigated the symptoms of the a reduction in output while driving on the road, or increasing of fumer out exhaust gas on inclined road while working air-conditioner in summer. Notice how the experiment in 2010, the Ministry of Environment(Chapter No. 2010-46), and how the vehicle emissions inspection was carried out. 2500cc Diesel cars used in the study were used and compare to output of engine, exhaust gas, inhalation temperature measurement Inhalation of cold air has not been supplied to all agencies when comparing the results when cold air intake temperature of the supply air-conditioning switch range control from 1 to 4, the temperature drops $98^{\circ}C$ to $78^{\circ}C$. At the momentum of switch level 4, output from 63ps to 66ps after the connection has increased 9.6 percent, the highest concentration of exhaust emissions were reduced by 42.8%. This research can contribute in part to the reduction of exhaust directly supply into the cooling air intake line, doing the output of diesel cars in the summer. In addition, construction equipment and machinery that are currently being used excluding the engine's intercooler cooling of the supply line via a separate output in the summer and help reduce exhaust emissions is expected.

저전력 저잡음 클록 합성기 PLL 설계 (Design of a Low-Power Low-Noise Clock Synthesizer PLL)

  • 박준규;심현철;박종태;유종근
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2006년 학술대회 논문집 정보 및 제어부문
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    • pp.479-481
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    • 2006
  • This paper describes a 2.5V, 320MHz low-noise and low-power Phase Locked Loop(PLL) using a noise-rejected Voltage Controlled ring Oscillator(VCO) fabricated in a TSMC 0.25um CMOS technology. In order to improve the power consumption and oscillation frequency of the PLL, The VCO consist of three-stage fully differential delay cells that can obtain the characteristic of high speed, low power and low phase noise. The VCO operates at 7MHz -670MHz. The oscillator consumes l.58mA from a 320MHz frequency and 2.5V supply. When the PLL with fully-differential ring VCO is locked 320MHz, the jitter and phase noise measured 26ps (rms), 157ps (p-p) and -97.09dB at 100kHz offset. We introduce and analysis the conditions in which ring VCO can oscillate for low-power operation.

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부하특성을 고려한 마그네트론 구동용 PS FB-ZVS PWM 컨버터의 설계 (A Design of PS FB-ZVS PWM Converter with Magnetron Load)

  • 이완윤;정교범;신판석
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 2001년도 전력전자학술대회 논문집
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    • pp.360-363
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    • 2001
  • The conventional 60(Hz) power supply for driving magnetron in microwave oven has disadvantages of heavy weight and low efficiency due to 60(Hz) High Voltage Transformer(HVT), capacitor and the phase control of thyristors with open-loop controller. To alleviate these disadvantages, this paper proposes a 20(kHz) phase-shifted(PS) Full-Bridge(FB) Zero- voltage-Switched(ZVS) PWM converter to drive a 600(W) magnetron in an 1(kW) microwave oven and to control the average anode current.

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8.2-GHz band radar RFICs for an 8 × 8 phased-array FMCW receiver developed with 65-nm CMOS technology

  • Han, Seon-Ho;Koo, Bon-Tae
    • ETRI Journal
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    • 제42권6호
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    • pp.943-950
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    • 2020
  • We propose 8.2-GHz band radar RFICs for an 8 × 8 phased-array frequency-modulated continuous-wave receiver developed using 65-nm CMOS technology. This receiver panel is constructed using a multichip solution comprising fabricated 2 × 2 low-noise amplifier phase-shifter (LNA-PS) chips and a 4ch RX front-end chip. The LNA-PS chip has a novel phase-shifter circuit for low-voltage operation, novel active single-to-differential/differential-to-single circuits, and a current-mode combiner to utilize a small area. The LNA-PS chip shows a power gain range of 5 dB to 20 dB per channel with gain control and a single-channel NF of 6.4 dB at maximum gain. The measured result of the chip shows 6-bit phase states with a 0.35° RMS phase error. The input P1 dB of the chip is approximately -27.5 dBm at high gain and is enough to cover the highest input power from the TX-to-RX leakage in the radar system. The gain range of the 4ch RX front-end chip is 9 dB to 30 dB per channel. The LNA-PS chip consumes 82 mA, and the 4ch RX front-end chip consumes 97 mA from a 1.2 V supply voltage. The chip sizes of the 2 × 2 LNA-PS and the 4ch RX front end are 2.39 mm × 1.3 mm and 2.42 mm × 1.62 mm, respectively.

A High-Resolution Dual-Loop Digital DLL

  • Kim, Jongsun;Han, Sang-woo
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제16권4호
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    • pp.520-527
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    • 2016
  • A new dual-loop digital delay-locked loop (DLL) using a hybrid (binary + sequential) search algorithm is presented to achieve both wide-range operation and high delay resolution. A new phase-interpolation range selector (PIRS) and a variable successive approximation register (VSAR) algorithm are adopted to resolve the boundary switching and harmonic locking problems of conventional digital DLLs. The proposed digital DLL, implemented in a $0.18-{\mu}m$ CMOS process, occupies an active area of $0.19mm^2$ and operates over a wide frequency range of 0.15-1.5 GHz. The DLL dissipates a power of 11.3 mW from a 1.8 V supply at 1 GHz. The measured peak-to-peak output clock jitter is 24 ps (effective pk-pk jitter = 16.5 ps) with an input clock jitter of 7.5 ps at 1.5 GHz. The delay resolution is only 2.2 ps.

경유의 저온특성에 따른 농용 디젤엔진의 저온시동성 (Starting of Farming Diesel Engines According to Characteristics of Light Oil at Low Temperature)

  • 신승엽;김학주;이용복;김병갑;윤진하;김기택;양대준
    • Journal of Biosystems Engineering
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    • 제28권1호
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    • pp.11-18
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    • 2003
  • This study was carried cut to get basic data of troubles in starting and supply of farm diesel engines in cold winter. The results of the study are summarized as follows: 1. As the result of farm survey. the proportions of farms which had starting problems or troubles in fuel supply in cold winter for the last 5 years were 38% for the farms with power-tillers and 32% for the farms with tractors. Most of the farms which had starting problems or troubles in fuel supply in cold winter used light oil for summer. spring or fall rather than for winter. 2. As the result of fuel supply test, fuel supply was stopped at -6$^{\circ}C$ and -18$^{\circ}C$ for summer light oil and winter light oil. respectively 3. The lowest temperatures of winter light oil for starting engine were -7.5$^{\circ}C$ for power-tiller. -12.5$^{\circ}C$ for tractor of 38ps, and -17.5$^{\circ}C$ for tractor of 45ps. which were 5~7.5$^{\circ}C$ lower than that of summer light oil. 4. The performance of engine starting and the trouble of fuel supply system at lower temperature were significantly improved by using winter hight oil rather than summer light oil.

광통신 모듈용 단일 칩 CMOS트랜시버의 구현 (Implementation of a Single Chip CMOS Transceiver for the Fiber Optic Modules)

  • 채상훈;김태련
    • 대한전자공학회논문지SD
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    • 제41권9호
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    • pp.11-17
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    • 2004
  • STM-1 체계의 광통신용 광모듈 송수신부에 내장하기 위한 155.52 Mbps 트랜시버 ASIC을 0.6 ㎛ 2-poly 3-metal 실리콘 CMOS 기술을 이용하여 구현하였다. 제작된 ASIC은 시스템에 의해서 처리된 155.52 Mbps 데이터 신호를 LD를 통하여 광신호로 변환하여 상대 시스템으로 송신하는 트랜스미터의 역할과, 상대 시스템으로부터 전송되어온 155.52 Mbps 광신호를 PD로 수신하여 전기신호로 변환하고 원형으로 복구하는 리시버의 역할을 한다. 트랜스미터와 리시버를 하나의 실리콘 기판에 집적하여 단일 칩 형태의 트랜시버를 설계하기 위하여, 잡음 및 상호 간섭 현상을 방지하기 위한 배치 상의 소자 격리 방법뿐만 아니라 전원분리, 가드링, 격리장벽 등을 도입한 새로운 설계 방법을 적용하였다. 설계된 칩의 크기는 4 × 4 ㎟이며, 루프백 측정에서 지터도 실효치 32.3 ps, 최대치 335.9 ps로 비교적 양호하게 나타났다. 전체 칩의 소비전력은 5V 단일전원 공급 상태에서 약 1.15 W(230 mA)로 나타났다.