• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.464-464
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• 2012

본 연구에서는 DBD (Dielectric Barrier Discharge)방식을 통해 발생된 대기압 plasma를 이용한 Photoresist (PR) Ashing에 관한 연구를 하였다. 사용된 DBD 반응기는 기존의 blank planar plate 형태의 Power가 인가되는 anode 부분과 Dielectric Barrier 사이 공간을 액상의 도전체로 채워 넣은 형태의 전극이 사용 하였으며, 인가 Power는 40 kHz AC 최대 인가 전압 15 kV를 사용 하였고(본 연구에서 인가 power는 30 KHz,전압 14 KV를 고정시킴) 플라즈마를 발생시 라디칼의 활성화를 유지하기 위해 전극 온도가 $180^{\circ}C$ 정하였다. Feeding 가스는 N2, 반응가스로는 CDA(Clean Dry Air), SF6와 CF4가스를 사용 하였으며 모든 공정은 In-line type으로 시편을 처리 하였다. CDA ratio의 경우에 질소대비 0.2%때 이송속도 30 mm/sec 1회 처리 기존 PR ashing은 최대 $320{\AA}$의 ashing 두께를 얻을 수 있었다. SF6와 CDA가스를 같이 반응하는 경우 ratio는 CDA : SF6 = 0.6% : 0.6%에서 PR ashing rate이 $841{\AA}/pass$의 값을 얻을 수 있었고, CDA가스만 첨가하는 경우보다 약2.6배 증가함을 관찰할 수 있었다. CF4 가스를 사용하는 경우 ratio는 CDA : CF4 = 0.2% : 0.2%에서 PR ashing rate이 $687{\AA}/pass$의 값을 얻을 수 있으며 CDA가스만 첨가하는 경우보다 약 2.1배 증가함을 관찰할 수 있었다. 그리고 PR ashing rate가 가스첨가종류와 비율에 따라서 변화함을 관찰하였고 최적조건을 찾기 위해 연구를 진행하였다. 추후 PR ashing rate가 향상을 하기 위해 가스혼합비율 및 stage 온도등 조건을 조절하여 공정최적조건을 얻기 위해 연구를 진행하였다.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.1500-1503
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• 2009

In this paper, we studied about atmospheric pressure remote plasma ashing of photoresist(PR), by using a modified dielectric barrier discharge(DBD). The effect of various gas combinations such as $N_2/O_2$, $N_2/O_2+SF_6$ on the changes PR ashing rate was investigated as a function of power. The maximum PR ashing rate of 1850 nm/min was achieved at $N_2$ (70 slm)/ $O_2$ (200 sccm) + $SF_6$ (3 slm). We found that as the oxygen and fluorine radical peaks were increased, the ashing rate is increased, too.

• 한국정보디스플레이학회:학술대회논문집
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• 2003.07a
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• pp.421-424
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• 2003

An AP plasma technology has been developed for the application of dry cleaner, PR ashing and PI rework in the large glass size. The technology is cost effective, environment friendly, and best fits for coming generation LCD production since the design is easily scalable to bigger size glasses. Surface cleaning results based on the contact angle study has been presented for $5^{th}$ generation LCD bare glass. PR ashing results and various parametric studies have been also presented.

• Transactions on Electrical and Electronic Materials
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• v.7 no.4
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• pp.204-209
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• 2006

Photo Resist (PR) ashing process was carried out with the atmospheric pressure- dielectric barrier discharge (ADBD) using $SF_6/N_2/O_2$. Ashing rate (AR) was sensitive to the mixing ratio of the oxygen and nitrogen of the blower type of ADBD asher. The maximum AR of 5000 A/min was achieved at 2% of oxygen in the $N_2$ plasma. With increasing the oxygen concentration to more than 2% in the $N_2$ plasma, the discharge becomes weak due to the high electron affinity of oxygen, resulting in the decrease of AR. When adding 0.5% of SF6 to $O_2/N_2$ mixed plasma, the PR AR increased drastically to 9000 A/min and the ashed surface of PR was smoother compared to the processed surface without $SF_6$. Carbon Fluorinated polymer may passivate the PR surface. It was also observed that the glass surface was not damaged by the fluorine.

• Journal of the Semiconductor & Display Technology
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• v.7 no.2
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• pp.35-38
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• 2008

This study shows the improvement of PR-Ashing rates in semi-conductor process using Atmospheric Plasma. Taguchi method is used to improve Ashing rates of photo-resist that is spread on the surface of a wafer. Improvement of Ashing rates is acquired through the decision of the effective factors and suitable combination of the factors. The results show the contribution rate of each factor and the effectiveness of Plasma for PR-Ashing process in this system.

• Journal of the Semiconductor & Display Technology
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• v.16 no.2
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• pp.55-60
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• 2017

The supercritical $CO_2$ (sc-$CO_2$) mixture and the sc-$CO_2$-based Photoresist(PR) stripping(SCPS) process were applied to the removal of the post etch/ash PR residue on aluminum patterned wafers and the results were observed by scanning of electron microscope(SEM). In the case of MDII wafers, the carbonized PR was able to be effectively removed without pre-stripping by oxygen plasma ashing by using sc-$CO_2$ mixture containing the optimum formulated additives at the proper pressure and temperature, and the same result was also able to be obtained in the case of HDII wafer. It was found that the efficiency of SCPS of ion implanted wafer improved as the temperature of SCPS was high, so a very large amount of MEA in the sc-$CO_2$ mixture could be reduced if the temperature could be increased at condition that a process permits, and the ion implanted photoresist(IIP) on the wafer was able to be removed completely without pre-treatment of plasma ashing by using the only 1 step SCPS process. By using SCPS process, PR polymers formed on sidewalls of metal conductive layers such as aluminum films, titanium and titanium nitride films by dry etching and ashing processes were removed effectively with the minimization of the corrosion of the metal conductive layers.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.4
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• pp.325-331
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• 2007

In this study, the inter-metal dielectric material of FSG was changed by low-k material in $0.13{\mu}m$ foundry-compatible technology (FCT) device process based on fluorinated silicate glass (FSG). Black diamond (BD) was used as a low-k material with a dielectric constant of 2.95 for optimization and yield-improvement of the low-k based device process. For yield-improvement in low-k based device process, some problems such as photoresist (PR) poisoning, damage of low-k in etch/ash/cleaning process, and chemical mechanical planarization (CMP) delamination must be solved. The PR poisoning was not observed in BD based device. The pressure in CMP process decreased to 2.8 psi to remove the CMP delamination for Cu-CMP and USG-CMP. $H_2O$ ashing process was selected instead of $O_2$ ashing process due to the lowest condition of low-k damage. NE14 cleaning after ashing process lot the removal of organic residues in vias and trenches was employed for wet process instead of dilute HF (DHF) process. The similar-state of SRAM yield was obtained in Cu/low-k process compared with the conventional $0.13{\mu}m$ FCT device by the optimization of these process conditions.

• Proceedings of the Korean Vacuum Society Conference
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• 2003.08a
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• pp.208-208
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• 2003

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.6
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• pp.1099-1103
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• 2007

TFT's have been intensively researched for possible electronic and display applications. Through tremendous engineering and scientific efforts, a-Si:H TFT fabrication process was greatly improved. In this paper, the reason on defects occurring at a-Si:H TFT fabrication process is analyzed and solved, so a-Si:H TFT's yield is increased and reliability is improved. The a-Si:H TFT of this paper is inverted staggered type TFT. The gate electrode is formed by patterning with length of $8{\mu}m{\sim}16{\mu}m$ and width of $80{\sim}200{\mu}m$ after depositing with gate electrode (Cr). We have fabricated a-SiN:H, conductor, etch-stopper and photo-resistor on gate electrode in sequence, respectively. We have deposited n+a-Si:H, NPR(Negative Photo Resister) layer after forming pattern of Cr gate electrode by etch-slower pattern. The NPR layer by inverting pattern of upper Sate electrode is patterned and the n+a-Si:H layer is etched by the NPR pattern. The NPR layer is removed. After Cr layer is deposited and patterned, the source-drain electrode is formed. The a-Si:H TFT made like this has problems at photo-lithography process caused by remains of PR. When sample is cleaned, this remains of PR makes thin chemical film on surface and damages device. Therefor, in order to improve this problem we added ashing process and cleaning process was enforced strictly. We can estimate that this method stabilizes fabrication process and makes to increase a-Si:H TFT's yield.

• Journal of the Korean Vacuum Society
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• v.5 no.2
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• pp.113-118
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• 1996

Aligning a cathode tip at the center of a gate hole is important in gated filed emission devices. We have fabricated a silicon field emitter using a following process so that a cathode and a gate hole are automatically aligned . After forming silicon tips on a silicon wafer, the wafer was covered with the $SiO_2$, gate metal, and photoresistive(PR) films. Because of the viscosity of the PR films, a spot where cathode tips were located protruded above the surface. By ashing the surface of the PR film, the gate metal above the tip apex was exposed when other area was still covered with the PR film. The exposed gate metal and subsequenlty the $SiO_2$ layer were selectively etched. The result produced a field emitter in which the gate film was in volcano shape and the cathode tip was located at the center of the gate hole. Computer simulation showed that the volcano shape and the cathode tip was located at the center of the gat hole. Computer simulation showed that the volcano shape emitter higher current and the electron beam which was focused better than the emitter for which the gate film was flat.